sram_32_128_scn4m_subm.html
Compiled at: 2020-06-24
DRC errors: skipped
LVS errors: skipped
Git commit id: 8166adc512f36a28a6334c995999ac60a5fe5388
Ports and Configuration
| Type | Value |
|---|---|
| WORD_SIZE | 32 |
| NUM_WORDS | 128 |
| NUM_BANKS | 1 |
| NUM_RW_PORTS | 1 |
| NUM_R_PORTS | 0 |
| NUM_W_PORTS | 0 |
| Area (µm2) | 0 |
Operating Conditions
| Parameter | Min | Typ | Max | Units |
|---|---|---|---|---|
| Power supply (VDD) range | 5.0 | 5.0 | 5.0 | Volts |
| Operating Temperature | 25 | 25 | 25 | Celsius |
| Operating Frequency (F) | 1757 | MHz |
Timing Data
Using analytical model: results may not be precise
| Parameter | Min | Max | Units |
|---|---|---|---|
| din0[31:0] setup rising | 0.009 | 0.009 | ns |
| din0[31:0] setup falling | 0.009 | 0.009 | ns |
| din0[31:0] hold rising | 0.001 | 0.001 | ns |
| din0[31:0] hold falling | 0.001 | 0.001 | ns |
| dout0[31:0] cell rise | 2.479 | 3.13 | ns |
| dout0[31:0] cell fall | 2.755 | 2.845 | ns |
| dout0[31:0] rise transition | 0.006 | 0.015 | ns |
| dout0[31:0] fall transition | 0.006 | 0.015 | ns |
| csb0 setup rising | 0.009 | 0.009 | ns |
| csb0 setup falling | 0.009 | 0.009 | ns |
| csb0 hold rising | 0.001 | 0.001 | ns |
| csb0 hold falling | 0.001 | 0.001 | ns |
| addr0[6:0] setup rising | 0.009 | 0.009 | ns |
| addr0[6:0] setup falling | 0.009 | 0.009 | ns |
| addr0[6:0] hold rising | 0.001 | 0.001 | ns |
| addr0[6:0] hold falling | 0.001 | 0.001 | ns |
| web0 setup rising | 0.009 | 0.009 | ns |
| web0 setup falling | 0.009 | 0.009 | ns |
| web0 hold rising | 0.001 | 0.001 | ns |
| web0 hold falling | 0.001 | 0.001 | ns |
Power Data
| Pins | Mode | Power | Units |
|---|---|---|---|
| !csb0 & clk0 & !web0 | Read Rising | 11.828 | mW |
| !csb0 & clk0 & !web0 | Read Falling | 11.828 | mW |
| !csb0 & !clk0 & web0 | Write Rising | 11.828 | mW |
| !csb0 & !clk0 & web0 | Write Falling | 11.828 | mW |
| csb0 | leakage | 0.004501 | mW |
Characterization Corners
| Transistor Type | Power Supply | Temperature | Corner Name |
|---|---|---|---|
| TT | 5.0 | 25 | _TT_5p0V_25C.lib |
| SS | 5.0 | 25 | _SS_5p0V_25C.lib |
| FF | 5.0 | 25 | _FF_5p0V_25C.lib |
Deliverables
| Type | Description | Link |
|---|---|---|
| .html | This datasheet | sram_32_128_scn4m_subm.html |
| .lib | Synthesis models | sram_32_128_scn4m_subm_TT_5p0V_25C.lib |
| .lib | Synthesis models | sram_32_128_scn4m_subm_SS_5p0V_25C.lib |
| .lib | Synthesis models | sram_32_128_scn4m_subm_FF_5p0V_25C.lib |
| .log | OpenRAM compile log | sram_32_128_scn4m_subm.log |
| .py | OpenRAM configuration file | sram_32_128_scn4m_subm.py |
| .sp | SPICE netlists | sram_32_128_scn4m_subm.sp |
| .v | Verilog simulation models | sram_32_128_scn4m_subm.v |