VLSIDAOpenRAM

sram_2_16_scn4m_subm.html

Compiled at: 2022-01-19

DRC errors: skipped

LVS errors: skipped

Git commit id: 06d391b3e365127628434b98044035232615f4b0

Ports and Configuration

TypeValue
WORD_SIZE2
NUM_WORDS16
NUM_BANKS1
NUM_RW_PORTS1
NUM_R_PORTS0
NUM_W_PORTS0
Area (µm2)0

Operating Conditions

ParameterMinTypMaxUnits
Power supply (VDD) range5.05.05.0Volts
Operating Temperature252525Celsius
Operating Frequency (F)200MHz

Timing Data

Using analytical model: results may not be precise

ParameterMinMaxUnits
din0[1:0] setup rising0.0090.009ns
din0[1:0] setup falling0.0090.009ns
din0[1:0] hold rising0.0010.001ns
din0[1:0] hold falling0.0010.001ns
dout0[1:0] cell rise1.2571.347ns
dout0[1:0] cell fall1.2571.347ns
dout0[1:0] rise transition0.0060.015ns
dout0[1:0] fall transition0.0060.015ns
csb0 setup rising0.0090.009ns
csb0 setup falling0.0090.009ns
csb0 hold rising0.0010.001ns
csb0 hold falling0.0010.001ns
addr0[3:0] setup rising0.0090.009ns
addr0[3:0] setup falling0.0090.009ns
addr0[3:0] hold rising0.0010.001ns
addr0[3:0] hold falling0.0010.001ns
web0 setup rising0.0090.009ns
web0 setup falling0.0090.009ns
web0 hold rising0.0010.001ns
web0 hold falling0.0010.001ns

Power Data

PinsModePowerUnits
!csb0 & clk0 & !web0Read Rising3.4010mW
!csb0 & clk0 & !web0Read Falling3.4010mW
!csb0 & !clk0 & web0Write Rising3.4010mW
!csb0 & !clk0 & web0Write Falling3.4010mW
csb0leakage0.000194mW

Characterization Corners

Transistor TypePower SupplyTemperatureCorner Name
TT5.025_TT_5p0V_25C.lib

Deliverables

TypeDescriptionLink
.htmlThis datasheetsram_2_16_scn4m_subm.html
.libSynthesis modelssram_2_16_scn4m_subm_TT_5p0V_25C.lib
.logOpenRAM compile logsram_2_16_scn4m_subm.log
.pyOpenRAM configuration filesram_2_16_scn4m_subm.py
.spSPICE netlistssram_2_16_scn4m_subm.sp
.vVerilog simulation modelssram_2_16_scn4m_subm.v