VLSIDAOpenRAM

sram_2_16_scn4m_subm.html

Compiled at: 2020-04-23

DRC errors: 0

LVS errors: 0

Git commit id: 6e070925b642691f412d5fc0fcce563edef9cd3f

Ports and Configuration

TypeValue
WORD_SIZE2
NUM_WORDS16
NUM_BANKS1
NUM_RW_PORTS1
NUM_R_PORTS0
NUM_W_PORTS0
Area (µm2)85520

Operating Conditions

ParameterMinTypMaxUnits
Power supply (VDD) range5.05.05.0Volts
Operating Temperature252525Celsius
Operating Frequency (F)110MHz

Timing Data

Using spice characterizer

ParameterMinMaxUnits
din0[1:0] setup rising0.1880.237ns
din0[1:0] setup falling0.1760.249ns
din0[1:0] hold rising-0.215-0.117ns
din0[1:0] hold falling-0.093-0.081ns
dout0[1:0] cell rise2.3892.849ns
dout0[1:0] cell fall2.3892.849ns
dout0[1:0] rise transition2.5162.635ns
dout0[1:0] fall transition2.5162.635ns
csb0 setup rising0.1880.237ns
csb0 setup falling0.1760.249ns
csb0 hold rising-0.215-0.117ns
csb0 hold falling-0.093-0.081ns
addr0[3:0] setup rising0.1880.237ns
addr0[3:0] setup falling0.1760.249ns
addr0[3:0] hold rising-0.215-0.117ns
addr0[3:0] hold falling-0.093-0.081ns
web0 setup rising0.1880.237ns
web0 setup falling0.1760.249ns
web0 hold rising-0.215-0.117ns
web0 hold falling-0.093-0.081ns

Power Data

PinsModePowerUnits
!csb0 & clk0 & !web0Read Rising6.8246mW
!csb0 & clk0 & !web0Read Falling6.8246mW
!csb0 & !clk0 & web0Write Rising6.9616mW
!csb0 & !clk0 & web0Write Falling6.9616mW
csb0leakage0.4069451mW

Characterization Corners

Transistor TypePower SupplyTemperatureCorner Name
TT5.025_TT_5p0V_25C.lib

Deliverables

TypeDescriptionLink
.gdsGDSII layout viewssram_2_16_scn4m_subm.gds
.htmlThis datasheetsram_2_16_scn4m_subm.html
.lefLEF filessram_2_16_scn4m_subm.lef
.libSynthesis modelssram_2_16_scn4m_subm_TT_5p0V_25C.lib
.logOpenRAM compile logsram_2_16_scn4m_subm.log
.pyOpenRAM configuration filesram_2_16_scn4m_subm.py
.spSPICE netlistssram_2_16_scn4m_subm.sp
.vVerilog simulation modelssram_2_16_scn4m_subm.v