sram_2_16_scn4m_subm.html
Compiled at: 2020-04-23
DRC errors: 0
LVS errors: 0
Git commit id: 6e070925b642691f412d5fc0fcce563edef9cd3f
Ports and Configuration
| Type | Value |
|---|---|
| WORD_SIZE | 2 |
| NUM_WORDS | 16 |
| NUM_BANKS | 1 |
| NUM_RW_PORTS | 1 |
| NUM_R_PORTS | 0 |
| NUM_W_PORTS | 0 |
| Area (µm2) | 85520 |
Operating Conditions
| Parameter | Min | Typ | Max | Units |
|---|---|---|---|---|
| Power supply (VDD) range | 5.0 | 5.0 | 5.0 | Volts |
| Operating Temperature | 25 | 25 | 25 | Celsius |
| Operating Frequency (F) | 110 | MHz |
Timing Data
Using spice characterizer
| Parameter | Min | Max | Units |
|---|---|---|---|
| din0[1:0] setup rising | 0.188 | 0.237 | ns |
| din0[1:0] setup falling | 0.176 | 0.249 | ns |
| din0[1:0] hold rising | -0.215 | -0.117 | ns |
| din0[1:0] hold falling | -0.093 | -0.081 | ns |
| dout0[1:0] cell rise | 2.389 | 2.849 | ns |
| dout0[1:0] cell fall | 2.389 | 2.849 | ns |
| dout0[1:0] rise transition | 2.516 | 2.635 | ns |
| dout0[1:0] fall transition | 2.516 | 2.635 | ns |
| csb0 setup rising | 0.188 | 0.237 | ns |
| csb0 setup falling | 0.176 | 0.249 | ns |
| csb0 hold rising | -0.215 | -0.117 | ns |
| csb0 hold falling | -0.093 | -0.081 | ns |
| addr0[3:0] setup rising | 0.188 | 0.237 | ns |
| addr0[3:0] setup falling | 0.176 | 0.249 | ns |
| addr0[3:0] hold rising | -0.215 | -0.117 | ns |
| addr0[3:0] hold falling | -0.093 | -0.081 | ns |
| web0 setup rising | 0.188 | 0.237 | ns |
| web0 setup falling | 0.176 | 0.249 | ns |
| web0 hold rising | -0.215 | -0.117 | ns |
| web0 hold falling | -0.093 | -0.081 | ns |
Power Data
| Pins | Mode | Power | Units |
|---|---|---|---|
| !csb0 & clk0 & !web0 | Read Rising | 6.8246 | mW |
| !csb0 & clk0 & !web0 | Read Falling | 6.8246 | mW |
| !csb0 & !clk0 & web0 | Write Rising | 6.9616 | mW |
| !csb0 & !clk0 & web0 | Write Falling | 6.9616 | mW |
| csb0 | leakage | 0.4069451 | mW |
Characterization Corners
| Transistor Type | Power Supply | Temperature | Corner Name |
|---|---|---|---|
| TT | 5.0 | 25 | _TT_5p0V_25C.lib |
Deliverables
| Type | Description | Link |
|---|---|---|
| .gds | GDSII layout views | sram_2_16_scn4m_subm.gds |
| .html | This datasheet | sram_2_16_scn4m_subm.html |
| .lef | LEF files | sram_2_16_scn4m_subm.lef |
| .lib | Synthesis models | sram_2_16_scn4m_subm_TT_5p0V_25C.lib |
| .log | OpenRAM compile log | sram_2_16_scn4m_subm.log |
| .py | OpenRAM configuration file | sram_2_16_scn4m_subm.py |
| .sp | SPICE netlists | sram_2_16_scn4m_subm.sp |
| .v | Verilog simulation models | sram_2_16_scn4m_subm.v |