A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
Updated 2026-04-24 13:52:52 +02:00
Netgen complete LVS tool for comparing SPICE or verilog netlists
Updated 2026-04-04 08:00:02 +02:00