Netgen complete LVS tool for comparing SPICE or verilog netlists
Updated 2026-07-07 08:00:05 +02:00
A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
Updated 2026-06-16 09:24:40 +02:00