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luke/ xschem

C 0 0 0

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Updated 2026-09-08 19:24:19 +02:00

luke/ ngspice

C 0 0 0

Updated 2026-09-07 22:36:36 +02:00

luke/ magic

C 0 0 0

Magic VLSI Layout Tool

Updated 2026-09-01 20:59:07 +02:00

luke/ riscv-gnu-toolchain

C 0 0 0

Updated 2026-08-26 12:01:26 +02:00

luke/ abc

C 0 0 0

ABC: System for Sequential Logic Synthesis and Formal Verification

Updated 2026-08-18 12:07:47 +02:00

luke/ netgen

C 0 0 0

Netgen complete LVS tool for comparing SPICE or verilog netlists

Updated 2026-07-07 08:00:05 +02:00