A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
Updated 2025-11-07 11:48:02 +01:00
Updated 2025-11-06 13:04:44 +01:00
Netgen complete LVS tool for comparing SPICE or verilog netlists
Updated 2025-10-24 08:00:04 +02:00