Updated 2025-12-23 11:58:13 +01:00
A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
Updated 2025-12-19 13:06:57 +01:00
Netgen complete LVS tool for comparing SPICE or verilog netlists
Updated 2025-12-12 08:00:03 +01:00