A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
Updated 2026-06-16 09:24:40 +02:00
ABC: System for Sequential Logic Synthesis and Formal Verification
Updated 2026-06-15 19:40:58 +02:00
Updated 2026-06-12 17:38:07 +02:00
Netgen complete LVS tool for comparing SPICE or verilog netlists
Updated 2026-06-09 08:00:04 +02:00