Updated 2026-02-09 17:01:19 +01:00
A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
Updated 2026-02-09 16:51:17 +01:00
Netgen complete LVS tool for comparing SPICE or verilog netlists
Updated 2026-02-03 08:00:02 +01:00