diff --git a/Migrating-from-Vivado.md b/Migrating-from-Vivado.md
index be317bf..9d56291 100644
--- a/Migrating-from-Vivado.md
+++ b/Migrating-from-Vivado.md
@@ -1,3 +1,5 @@
+**This page is WIP.**
+
 At this point it is not possible to work with Xilinx FPGAs by using only free software. If you are looking for a full free software toolchain for working with FPGAs, see [Project IceStorm](http://www.clifford.at/icestorm/).
 
 That being said, most of your workflow can still be done using Yosys, Icarus Verilog and other free software tools. You will have to use Vivado for place&route, bitstream generation and writing your bit file onto your device. However, all these can be done by using tcl scripts, meaning that you will not have to open Vivado GUI at all.