From aa9889a18366c23fde231fcd12de8852b24f4aa2 Mon Sep 17 00:00:00 2001 From: gatecat Date: Mon, 8 Nov 2021 15:26:34 +0000 Subject: [PATCH] Updated FPGA family feature matrix (markdown) --- FPGA-family-feature-matrix.md | 40 +++++++++++++++++------------------ 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/FPGA-family-feature-matrix.md b/FPGA-family-feature-matrix.md index c80c533..fb3926f 100644 --- a/FPGA-family-feature-matrix.md +++ b/FPGA-family-feature-matrix.md @@ -4,26 +4,26 @@ There is a growing number of FPGA families that have support in the open source The table on this page aims to keep track of which FPGA primitives are supported by which project. -| FPGA Family | Gowin LittleBee | MachXO2 | Lattice ECP5 | Lattice Nexus | -|----------------|-----------------|----------------|-----------------|----------------| -| Project | Apicula |Facade/Trellis | Trellis | prjoxide | -| Logic Slice | ✔️ |✔️ |✔️ |✔️ | -| ├ LUTRAM | ❌ |❌ |✔️ |✔️ | -| └ ALU | ✔️ |❌ |✔️ |✔️ | -| IO buffer | ✔️ |✔️ |✔️ |✔️ | -| ├ IO standards | ✔️ |⚠️ |✔️ |🚧 | -| └ DDR/SERDES | ❌ |❌ |✔️ |🚧 | -| Block RAM | ❌ |❌ |✔️ |✔️ | -| DSP | ❌ |❌ |✔️ |✔️ | -| PLL | ❌ |❌ |✔️ |⚠️ | -| Routing | ✔️ |✔️ |✔️ |✔️ | -| ├ Local | ✔️ |✔️ |✔️ |✔️ | -| ├ Global | ✔️ |🚧 |✔️ |✔️ | -| └ Long wires | ❌ |❌ (N/A) |❌ (N/A) |❌ (N/A) | -| Timing | ✔️ |❌ |✔️ |✔️ | -| ├ Logic | ✔️ |❌ |✔️ |✔️ | -| ├ Routing | ✔️ |❌ |✔️ |✔️ | -| └ IO buffer | ✔️ |❌ |🚧 |🚧 | +| FPGA Family | Gowin LittleBee | MachXO2 | Lattice ECP5 | Lattice Nexus | Lattice iCE40 | +|----------------|-----------------|----------------|-----------------|----------------|----------------| +| Project | Apicula |Facade/Trellis | Trellis | prjoxide | Icestorm | +| Logic Slice | ✔️ |✔️ |✔️ |✔️ |✔️ | +| ├ LUTRAM | ❌ |❌ |✔️ |✔️ |❌ (N/A) | +| └ ALU | ✔️ |❌ |✔️ |✔️ |✔️ | +| IO buffer | ✔️ |✔️ |✔️ |✔️ |✔️ | +| ├ IO standards | ✔️ |⚠️ |✔️ |🚧 |✔️ | +| └ DDR/SERDES | ❌ |❌ |✔️ |🚧 |✔️ | +| Block RAM | ❌ |❌ |✔️ |✔️ |✔️ | +| DSP | ❌ |❌ |✔️ |✔️ |✔️ (up5k only) | +| PLL | ❌ |❌ |✔️ |⚠️ |✔️ | +| Routing | ✔️ |✔️ |✔️ |✔️ |✔️ | +| ├ Local | ✔️ |✔️ |✔️ |✔️ |✔️ | +| ├ Global | ✔️ |🚧 |✔️ |✔️ |✔️ | +| └ Long wires | ❌ |❌ (N/A) |❌ (N/A) |❌ (N/A) |❌ (N/A) | +| Timing | ✔️ |❌ |✔️ |✔️ |✔️ | +| ├ Logic | ✔️ |❌ |✔️ |✔️ |✔️ | +| ├ Routing | ✔️ |❌ |✔️ |✔️ |✔️ | +| └ IO buffer | ✔️ |❌ |🚧 |🚧 |❌ | | symbol | meaning | |--------|--------------------------------------|