# -script +cmd,arg;cmd
read_verilog <<EOT
module top(input [7:0] a, b, output [7:0] y, output c);
	assign {c, y} = a + b;
endmodule
EOT

hierarchy -top top
proc
opt
design -save gold

techmap
opt
logger -expect log "\+ &if -g -K 6" 1
abc_new -liberty openroad/cm_test_cells.lib -script +&st;&if,-g,-K,6;&nf
logger -check-expected
select -assert-none t:$_*_
check -assert

read_verilog openroad/cells_sim.v
flatten
opt_clean
design -stash gate
design -copy-from gold -as gold top
design -copy-from gate -as gate top
miter -equiv -flatten -make_assert gold gate miter
sat -verify -prove-asserts -show-ports miter