# Assert against abc synth with and without csa, hopefully prevent regressions
# Baseline
read_verilog <<EOT
module bench(
	input [7:0] a, b, c, d, e, f, g, h,
	output [7:0] y
);
	assign y = a + b + c + d + e + f + g + h;
endmodule
EOT
hierarchy -auto-top
proc
opt
techmap
abc -g AND,OR,XOR
select -assert-min 236 t:$_AND_ t:$_OR_ t:$_XOR_ %u
design -reset

# With csa_tree
read_verilog <<EOT
module bench(
	input [7:0] a, b, c, d, e, f, g, h,
	output [7:0] y
);
	assign y = a + b + c + d + e + f + g + h;
endmodule
EOT
hierarchy -auto-top
proc
opt
csa_tree
techmap
abc -g AND,OR,XOR
select -assert-max 235 t:$_AND_ t:$_OR_ t:$_XOR_ %u
design -reset

# Depth-otimal baseline
read_verilog <<EOT
module bench(
	input [7:0] a, b, c, d, e, f, g, h,
	output [7:0] y
);
	assign y = a + b + c + d + e + f + g + h;
endmodule
EOT
hierarchy -auto-top
proc
opt
techmap
abc -D 1
select -assert-min 240 t:$_AND_ t:$_NAND_ t:$_OR_ t:$_NOR_ t:$_XOR_ t:$_XNOR_ t:$_NOT_ %u
design -reset

# Depth-optimal with csa_tree
read_verilog <<EOT
module bench(
	input [7:0] a, b, c, d, e, f, g, h,
	output [7:0] y
);
	assign y = a + b + c + d + e + f + g + h;
endmodule
EOT
hierarchy -auto-top
proc
opt
csa_tree
techmap
abc -D 1
select -assert-max 236 t:$_AND_ t:$_NAND_ t:$_OR_ t:$_NOR_ t:$_XOR_ t:$_XNOR_ t:$_NOT_ %u
design -reset