4512 Commits

Author	SHA1	Message	Date
Peter Gadfort	9534f4ab80	check if characters are found and use size if not	2025-01-29 15:56:05 -05:00
Martin Povišer	6c76dcec3e	macc_v2: Fix v2 omissions	2025-01-27 13:08:44 +01:00
Martin Povišer	61450e8b6e	Update codebase for macc_v2	2025-01-24 12:38:03 +01:00
Martin Povišer	c5fd96ebb0	macc_v2: Start new cell	2025-01-24 12:38:03 +01:00
Peter Gadfort	66545caa1b	Merge branch 'main' into synth-flatten	2025-01-20 10:24:38 -07:00
Peter Gadfort	f0860459ac	add support for using scratchpad value for flatten.separator in flatten command	2025-01-18 10:45:19 -07:00
N. Engelhardt	a5ba1d2eba	fix bugs in handling last id in hdlname to scopename conversion	2025-01-16 12:57:08 +01:00
N. Engelhardt	d640157ec4	fix some cases of hdlname being added to objects with private names	2025-01-15 15:56:42 +01:00
Emil J. Tywoniak	a58481e9b7	mark all hash_into methods nodiscard	2025-01-14 12:39:15 +01:00
Martin Povišer	6225abec71	Merge pull request #4839 from mikesinouye/separator ... Add option for a custom flatten block separator char	2025-01-13 15:51:31 +01:00
Larry Doolittle	27be9a6b77	keep_hierarchy.cc: use strictly correct syntax for printf of uint64_t values ... Removes two warnings from the compile, at least on amd64 arch	2025-01-10 14:03:09 -08:00
mikesinouye	13b183c9c5	Add option for a custom flatten block separator char	2025-01-09 18:30:23 -08:00
Martin Povišer	ca0ace66bc	Merge pull request #4817 from povik/macc_v2-1 ... macc: Stop using the B port	2025-01-08 14:42:51 +01:00
Martin Povišer	366e3f22fb	Merge pull request #4836 from YosysHQ/emil/share-fix-log ... share: fix misleading 0 cells log message	2025-01-08 13:14:34 +01:00
Martin Povišer	652a1b9806	macc: Stop using the B port ... The B port is for single-bit summands. These can just as well be represented as an additional summand on the A port (which supports summands of arbitrary width). An upcoming `$macc_v2` cell won't be special-casing single-bit summands in any way. In preparation, make the following changes: * remove the `bit_ports` field from the `Macc` helper (instead add any single-bit summands to `ports` next to other summands) * leave `B` empty on cells emitted from `Macc::to_cell`	2025-01-08 13:03:35 +01:00
Emil J. Tywoniak	1836a571c9	share: fix misleading log message	2025-01-07 19:25:15 +01:00
Martin Povišer	41e4aa8f0a	Merge pull request #4819 from povik/wreduce-resign ... wreduce: Optimize signedness when possible	2025-01-06 15:27:55 +01:00
Martin Povišer	be351886a5	wreduce: Adjust naming and comments	2025-01-03 12:54:34 +01:00
Emil J. Tywoniak	b9b9515bb0	hashlib: hash_eat -> hash_into	2024-12-18 15:09:25 +01:00
Emil J. Tywoniak	4e29ec1854	hashlib: acc -> eat	2024-12-18 15:09:25 +01:00
Emil J. Tywoniak	c73c88033d	hashlib: only include in one place	2024-12-18 14:58:31 +01:00
Emil J. Tywoniak	c10b3f57e1	abc: sort stats	2024-12-18 14:58:31 +01:00
Emil J. Tywoniak	d071489ab1	hashlib: redo interface for flexibility	2024-12-18 14:49:25 +01:00
Martin Povišer	08778917db	wreduce: Optimize signedness when possible	2024-12-16 12:57:08 +01:00
Martin Povišer	4bd6061709	Merge pull request #4799 from povik/wrapcell-unused ... wrapcell: Optionally track unused outputs	2024-12-10 21:16:28 +01:00
Martin Povišer	f7ad003a6f	Merge pull request #4802 from povik/abc9-box-repeat ... Adjust `abc9_ops -prep_box` to allow repeated invocation	2024-12-10 20:08:17 +01:00
Martin Povišer	3cd01a57cd	wrapcell: Add comments, const qualifier	2024-12-10 15:13:31 +01:00
Martin Povišer	0bb139dc25	abc_new: Fix help crash	2024-12-10 14:27:55 +01:00
Martin Povišer	2a3f60bc06	abc_new: Support `abc9_box` mode on ordinary design hierarchy ... Previously the `abc9_box` mode was reserved to modules with the `blackbox` or `whitebox` attribute. Allow `abc9_box` on ordinary modules when doing hierarchical synthesis.	2024-12-10 14:27:29 +01:00
Martin Povišer	285f24d764	abc_new: Support per-module script override	2024-12-10 14:27:29 +01:00
Martin Povišer	9161377c5a	wrapcell: Fix help	2024-12-09 15:40:33 +01:00
Martin Povišer	481162b848	Merge pull request #4800 from povik/portarcs-fix ... Fix portarcs edge cases	2024-12-09 15:13:15 +01:00
N. Engelhardt	8557455411	handle quotes and check return value	2024-12-06 11:25:45 +01:00
Miodrag Milanovic	1b403b82d7	Handle setting environment on Windows	2024-12-06 11:25:45 +01:00
N. Engelhardt	8b0f665cc5	add setenv pass	2024-12-06 11:25:43 +01:00
Martin Povišer	f3f8037328	abc9_ops: Allow no arcs on box w/o inputs or w/o outputs	2024-12-05 18:32:41 +01:00
Martin Povišer	481d596c43	abc9_ops -prep_box: Adjust for repeated invocation ... `abc9_ops -prep_box` command interprets the `abc9_box` attribute and prepares a .box file for ABC consumption. Previously this command was removing the attribute as it was processing each module which prevented repeated invocation of this command unless the box definitions were refreshed from a source file. Also the command was keeping existing `abc9_box_id` attributes instead of overwriting them with values from a new number sequence. Change both behaviors to allow repeated invocations of the command on the same design.	2024-12-05 18:32:41 +01:00
Martin Povišer	f4f65493a1	portarcs: Fix confusing disconnected and zero-delay case	2024-12-05 18:27:44 +01:00
Martin Povišer	2c66557d22	portarcs: Fix for case of unused gates	2024-12-05 18:27:43 +01:00
Martin Povišer	d57d21e566	wrapcell: Optionally track unused outputs	2024-12-05 18:16:53 +01:00
KrystalDelusion	c96d02b204	Merge pull request #4784 from YosysHQ/krys/reduce_warnings ... Reduce number of warnings	2024-12-05 09:16:06 +13:00
Martin Povišer	59a96470df	Merge pull request #4773 from povik/wrapcell ... wrapcell: Add new command	2024-12-04 11:49:51 +01:00
Martin Povišer	14ee5ce800	Merge pull request #4787 from povik/booth-macc ... booth: Map simple `$macc` instances too	2024-12-04 11:49:34 +01:00
Emil J	3b8e8ee012	Merge pull request #4797 from YosysHQ/emil/multiple-liberty ... Allow multiple -liberty args in dfflibmap and clockgate	2024-12-04 11:18:52 +01:00
Martin Povišer	384c191192	Merge pull request #4775 from povik/dont_map ... techmap: Add `-dont_map` for selective disabling of rules	2024-12-03 20:21:47 +01:00
Martin Povišer	1c7bb700c9	techmap: Rephrase help	2024-12-03 20:20:00 +01:00
Emil J. Tywoniak	6edf9c86cb	libparse: add LibertyMergedCells, enable multiple -liberty args for dfflibmap and clockgate	2024-12-03 17:36:00 +01:00
Emil J. Tywoniak	60fb241cb3	clockgate: clean up argument parsing	2024-12-03 17:35:10 +01:00
Martin Povišer	109d97bb40	Merge pull request #4706 from povik/keep_hierarchy-adjustalgo ... Adjust `keep_hierarchy` behavior	2024-12-03 12:18:28 +01:00
Martin Povišer	6ad4918121	Account for pre-existing `keep_hierarchy` in cost sum	2024-12-03 11:11:59 +01:00
Martin Povišer	c33f7b92f7	Fix typo	2024-12-03 11:11:02 +01:00
KrystalDelusion	889894a6d2	Merge pull request #4790 from YosysHQ/emil/clockgate-warnings ... clockgate: reduce build warnings	2024-12-03 13:25:52 +13:00
Lofty	fd05f73d50	dfflibmap: demote some warnings to debug	2024-12-02 14:17:51 +00:00
Emil J. Tywoniak	6b006e5f61	clockgate: reduce build warnings	2024-12-02 10:07:01 +01:00
Martin Povišer	1ded817beb	booth: Map simple `$macc` instances too	2024-12-01 16:00:04 +01:00
Krystine Sherwin	1de5d98ae2	Reduce comparisons of size_t and int ... `Const::size()` returns int, so change iterators that use it to `auto` instead of `size_t`. For cases where size is being explicitly cast to `int`, use the wrapper that we already have instead: `Yosys::GetSize()`.	2024-11-29 12:53:29 +13:00
Martin Povišer	956313efe8	Merge pull request #4742 from YosysHQ/hierarchy_notify_top_attr ... Print a note about finding attribute (* top *) in hierarchy	2024-11-28 00:07:18 +01:00
Martin Povišer	2962f8fa88	techmap: Add `-dont_map` for selective disabling of rules	2024-11-27 15:54:37 +01:00
Martin Povišer	79e9258a31	wrapcell: Add new command	2024-11-27 14:01:00 +01:00
Emil J	5b6baa3ef1	Merge pull request #4744 from YosysHQ/emil/clockgate-liberty ... clockgate: add -liberty	2024-11-20 15:04:00 +01:00
Emil J	56b80bdd22	Merge pull request #4448 from georgerennie/shiftadd_gating ... peepopt shiftadd: Only match for sufficiently small constant widths	2024-11-20 13:34:09 +01:00
Emil J	cc17d5bb70	Merge pull request #4612 from georgerennie/george/opt_demorgan_zero_width ... opt_demorgan: skip zero width cells	2024-11-20 13:33:16 +01:00
Emil J	18459b4b09	Merge pull request #4614 from georgerennie/george/opt_reduce_cell_width ... opt_reduce: keep at least one input to $reduce_or/and cells	2024-11-20 13:33:04 +01:00
Martin Povišer	7ebe451f9a	Merge pull request #4714 from georgerennie/george/proc_dff_bug_multiple_sigs ... proc_dff: fix early return bug	2024-11-20 13:26:32 +01:00
Emil J. Tywoniak	4d96cbec75	clockgate: reduce errors to warnings	2024-11-18 18:32:18 +01:00
Emil J. Tywoniak	983c54c75f	clockgate: help string add -dont_use and -liberty	2024-11-18 13:57:49 +01:00
Emil J. Tywoniak	a5bc36f77e	clockgate: add -dont_use	2024-11-18 13:45:30 +01:00
Emil J. Tywoniak	e6793da9a0	clockgate: refactor	2024-11-18 12:50:25 +01:00
Emil J. Tywoniak	45880ea7f2	clockgate: add -liberty	2024-11-14 20:37:59 +01:00
Lofty	d9ef388fcc	Merge pull request #4698 from YosysHQ/lofty/dfflibmap-enable ... dfflibmap: enable inference	2024-11-13 17:50:17 +00:00
Lofty	4f40187759	dfflibmap: move expression code into libparse	2024-11-13 16:06:57 +00:00
Lofty	08ed2c765e	dfflibmap: enable inference	2024-11-13 15:57:45 +00:00
Martin Povišer	2dba345049	portarcs: New command to derive propagation arcs	2024-11-13 16:20:35 +01:00
Martin Povišer	4ce8c7a0d3	Merge pull request #4709 from YosysHQ/emil/idstring-in-fold ... functional, glift: use fold overload of IdString::in instead of pool …	2024-11-13 15:17:33 +01:00
Martin Povišer	9da7341003	Merge pull request #4727 from georgerennie/george/bufnorm_constants2 ... bufnorm: preserve constant bits when mapping back to connections	2024-11-13 14:32:15 +01:00
N. Engelhardt	96c526d1ba	Print a note about finding attribute (* top *) in hierarchy	2024-11-13 10:21:44 +01:00
Martin Povišer	915df16c84	Merge pull request #4728 from YosysHQ/emil/fix-filterlib-roundtrip ... filterlib: preserve value quotes	2024-11-12 10:54:35 +01:00
Emil J. Tywoniak	49e1597ea4	filterlib: preserve value quotes	2024-11-12 01:21:07 +01:00
George Rennie	ff6c9446c0	bufnorm: preserve constant bits when mapping back to connections	2024-11-12 01:05:15 +01:00
Martin Povišer	1b1a6c4aed	Merge pull request #4525 from georgerennie/peepopt_clock_gate ... peepopt: Add formal opt to rewrite latches to ffs in clock gates	2024-11-11 14:49:09 +01:00
mszelwiga	8e508f2a2a	Fix setting bits of parameters in setundef pass ... This commit also adds test that verifies correctness of this change.	2024-11-08 17:03:08 +01:00
George Rennie	8f6058a7d6	bufnorm: preserve constant bits driving wires	2024-11-07 11:48:48 +01:00
George Rennie	626dbbe1e0	proc_dff: fix early return bug ... * early return caused proc_dff to stop considering rules after seeing one async rule - this is because continue should have been used to continue to procecssing the next rule instead of returning from the function	2024-11-07 00:06:03 +01:00
Emil J. Tywoniak	387a235158	functional, glift: use fold overload of IdString::in instead of pool literals	2024-11-06 12:48:32 +01:00
Martin Povišer	29af057430	Merge pull request #4707 from povik/stat-unused ... stat: Drop unused field	2024-11-05 09:38:29 +01:00
Martin Povišer	4df3a5d7ec	stat: Drop unused field	2024-11-05 09:37:35 +01:00
Martin Povišer	c8fffce2b5	keep_hierarchy: Update messages	2024-11-05 09:03:01 +01:00
Martin Povišer	cf79630be0	keep_hierarchy: Require size information on blackboxes	2024-11-05 09:02:36 +01:00
Martin Povišer	2425352551	keep_hierarchy: Redo hierarchy traversal for `-min_cost`	2024-11-05 09:02:36 +01:00
Lofty	3250f2b82b	Merge pull request #4700 from povik/select-list-mod ... Add `select -list-mod`	2024-11-04 15:38:42 +00:00
Martin Povišer	cbe73c9047	cellmatch: Visit whiteboxes for `-derive_luts`	2024-11-04 14:28:46 +01:00
Martin Povišer	c9ed6d8dcf	cellmatch: Rename `-lut_attrs` to `-derive_luts`; document option	2024-11-04 14:28:40 +01:00
Martin Povišer	35a20da512	logger: Adjust print	2024-11-04 13:16:40 +01:00
Martin Povišer	7aa3fdab80	select: Add `-list-mod` option	2024-11-04 13:16:13 +01:00
Lofty	dd7ea0ab6c	qwp: remove	2024-10-25 14:09:58 +01:00
Martin Povišer	9432e972f7	Merge pull request #4626 from povik/select-t-at ... select: Add new `t:@<name>` syntax	2024-10-16 10:18:05 +02:00
Martin Povišer	09be0351ce	select: Add new `t:@<name>` syntax	2024-10-15 12:22:02 +02:00
Emil J. Tywoniak	785bd44da7	rtlil: represent Const strings as std::string	2024-10-14 06:28:12 +02:00
Martin Povišer	a00137c2f6	Merge pull request #4625 from povik/cellmatch-lut ... cellmatch: Size the `lut` attribute	2024-10-11 14:08:55 +02:00
KrystalDelusion	0be3b7de51	Merge pull request #4635 from YosysHQ/krys/pr_docs_ci ... Remove make docs race conditions (and other docs fixes)	2024-10-08 21:39:30 +13:00
Miodrag Milanovic	f079772ade	Add TODO for missing help messages	2024-10-08 08:47:51 +02:00
Martin Povišer	9479d3bd3c	Merge pull request #4637 from YosysHQ/emil/bufnorm-warning ... bufnorm: avoid warning. NFC	2024-10-07 18:01:42 +02:00
Emil J. Tywoniak	a76bcdc58f	bufnorm: avoid remove warning. NFC	2024-10-07 17:58:48 +02:00
Martin Povišer	74e92d10e8	Merge pull request #4593 from povik/aiger2 ... New aiger backend	2024-10-07 16:11:25 +02:00
Martin Povišer	2e587c835f	abc9_exe: Document SC mapping options	2024-10-07 12:03:49 +02:00
Martin Povišer	3b6dcc7bd0	abc9_exe: Remove `-genlib` option	2024-10-07 12:03:49 +02:00
Martin Povišer	e0a86d5483	abc_new: Start new command for aiger2-based round trip	2024-10-07 12:03:49 +02:00
Martin Povišer	e58a9b6ab6	abc9: Understand ASIC options similar to `abc`	2024-10-07 12:03:48 +02:00
Martin Povišer	ec42b42bd9	cellmatch: Size the `lut` attribute	2024-10-02 11:29:54 +02:00
Mike A.	95a2099c90	Allow whitespace in `tee` command paths	2024-09-29 17:15:59 +02:00
George Rennie	023f029dcf	opt_reduce: keep at least one input to $reduce_or/and cells	2024-09-25 16:21:19 +01:00
George Rennie	58af70624f	opt_demorgan: skip zero width cells	2024-09-24 14:24:59 +01:00
N. Engelhardt	8e1e2b9a39	Merge pull request #4495 from povik/check-avert-costly-detail	2024-09-23 15:19:48 +02:00
Martin Povišer	38de01807e	Mark `bufnorm` experimental	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	80119386c0	Add RTLIL "buffered-normalized mode" and improve "bufnorm" pass ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	8bb70bac8d	Improvements in "bufnorm" pass ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	d027ead4b5	Improvements in "bufnorm" pass ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	f4b7ea5fb3	Improvements in "bufnorm" pass ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	32808a0393	Improvements and fixes to "bufnorm" cmd ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	d0b5dfa6ef	Add bufnorm pass ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Emil J	52382c6544	Merge pull request #4583 from YosysHQ/emil/clock_gate ... clockgate: centralize clock enables out of FFs	2024-09-16 15:41:01 +02:00
Emil J. Tywoniak	f193bcf683	clockgate: help string	2024-09-16 14:20:33 +02:00
Emil J. Tywoniak	be7c93ec6d	clockgate: 1-bit const 0	2024-09-16 13:58:27 +02:00
Emil J	a8a92d3469	clockgate: help string ... Co-authored-by: Martin Povišer <povik@cutebit.org>	2024-09-16 13:55:53 +02:00
N. Engelhardt	c8b42b7d48	Merge pull request #4538 from RCoeurjoly/verific_bounds	2024-09-12 13:04:04 +02:00
Emil J. Tywoniak	1e999a3cb7	clockgate: EN can be a bit on a multi-bit wire	2024-09-11 19:18:25 +02:00
Martin Povišer	34572708d5	Merge pull request #4595 from YosysHQ/emil/internal_stats-astnode ... internal_stats: astnode (sizeof)	2024-09-11 12:21:29 +02:00
Emil J. Tywoniak	1372c47036	internal_stats: astnode (sizeof)	2024-09-11 11:34:20 +02:00
Emil J. Tywoniak	8b464341c2	clockgate: no initvals	2024-09-11 10:24:48 +02:00
Roland Coeurjoly	bdc43c6592	Add left and right bound properties to wire. Add test. Fix printing ... for signed attributes Co-authored-by: N. Engelhardt <nak@yosyshq.com> Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>	2024-09-10 12:52:42 +02:00
Emil J. Tywoniak	7e473299bd	clockgate: bail on constant signals	2024-09-09 21:20:19 +02:00
Emil J. Tywoniak	e64fceef70	clockgate: prototype clock gating	2024-09-09 15:00:54 +02:00
Hoa Nguyen	c1205ebc42	Initialize area stats in stat pass ... Currently, the area variables in the stat struct are not initialized. This caused the area stats occasionally being an erroneous value. Signed-off-by: Hoa Nguyen <hnpl@google.com>	2024-09-07 21:30:58 -07:00
Miodrag Milanović	b20df72e1e	Merge pull request #4536 from YosysHQ/functional ... Functional Backend	2024-09-06 10:05:04 +02:00
Emil J. Tywoniak	14b9155492	internal_stats: fix doc build by adding a help string	2024-09-05 11:22:21 +02:00
Martin Povišer	68fbca8769	Merge pull request #4554 from YosysHQ/emil/devstat ... internal_stats: init, report current memory consumption on linux and mac	2024-09-03 21:06:46 +02:00
Emil J. Tywoniak	0ce7631956	internal_stats: init, report current memory consumption on linux and mac	2024-09-03 19:28:24 +02:00
George Rennie	bdb5d45591	proc_dff: respect sync rule priorities when generating complex dffsrs ... * This fixes #4560, where previously the order that sync rules were processed in depended on the order they were pulled out of a std::map. This PR changes this to process them in the order they are found in, respecting the priorities among the async signals	2024-08-28 15:48:07 +01:00
N. Engelhardt	0fc5812dcd	Merge pull request #4541 from YosysHQ/krys/compiler-warnings ... Resolve (some) compiler warnings	2024-08-26 15:04:16 +02:00
Emily Schmidt	850b3a6c29	convert class FunctionalIR to a namespace Functional, rename functionalir.h to functional.h, rename functional.h to compute_graph.h	2024-08-21 11:04:08 +01:00
Emily Schmidt	8c0f625c3a	functional backend: topological sort starts with the output and next states nodes, other nodes get deleted	2024-08-21 11:03:29 +01:00
Emily Schmidt	bdb59ffc8e	add -fst-noinit flag to sim for not initializing the state from the fst file	2024-08-21 11:03:29 +01:00
Emily Schmidt	dd5ec84a26	fix bugs in drivertools	2024-08-21 11:01:09 +01:00
Jannis Harder	d4e3daa9d0	ComputeGraph datatype for the upcoming functional backend	2024-08-21 11:01:09 +01:00
Jannis Harder	68c3a47945	WIP temporary drivertools example	2024-08-21 11:01:08 +01:00
Emil J	e0d3bbf3c3	Merge pull request #4452 from phsauter/shiftadd-underflow-fix ... peepopt: avoid shift-amount underflow	2024-08-19 15:45:46 +02:00
Krystine Sherwin	7b47f645d7	Address warnings ... - Setting default values - Fixing mismatched types - Guarding unused var	2024-08-16 04:30:31 +12:00
Martin Povišer	3057c13a66	Improve libparse encapsulation	2024-08-13 18:47:36 +02:00
Martin Povišer	78382eaa6f	libparse: Adjust whitespace	2024-08-13 18:47:36 +02:00
Martin Povišer	4c3203866f	exec: Add missing newline	2024-08-07 13:02:00 +02:00
George Rennie	236c69bed4	clk2fflogic: run peepopt -formalclk before processing design ... * this attempts to rewrite clock gating patterns into a form that is less likely to introduce combinational loops with clk2fflogic * can be disabled with -nopeepopt which is useful for testing clk2fflogic	2024-08-07 10:14:04 +01:00
George Rennie	2cb3b6e9b8	peepopt: add formal only peepopt to rewrite latches to ffs in clock gates ... * this is gated behind the -formalclk flag, which also disables the other synthesis focused optimizations	2024-08-07 10:01:45 +01:00
Miodrag Milanovic	6d98418f3d	Set ranges on exported wires in VCD and FST	2024-08-02 15:23:00 +02:00
Emil J	92cac63845	Merge pull request #4344 from widlarizer/emil/keep_hierarchy ... cost: add keep_hierarchy pass with min_cost argument	2024-07-29 16:33:08 +02:00
N. Engelhardt	9f869b265c	Merge pull request #4474 from tony-min-1/mchp ... Add PolarFire FPGA support	2024-07-29 15:28:44 +02:00
Emil J. Tywoniak	4b29f64142	cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter	2024-07-29 10:26:02 +02:00
N. Engelhardt	dd3637f9f0	Merge pull request #4506 from povik/synthprop-formatting ... synthprop: Reformat the help	2024-07-26 12:28:09 +02:00
Martin Povišer	7ee685a0b0	proc_rom: Set `src` on the emitted memory	2024-07-25 23:14:27 +01:00
Martin Povišer	e063b96104	synthprop: Reformat the help	2024-07-25 11:43:58 +02:00
Martin Povišer	0cefe8a1e8	check: Skip detailed edge modeling if costly	2024-07-18 13:08:19 +02:00
Martin Povišer	e70b1251ad	check: Adjust prints	2024-07-18 13:08:19 +02:00
Martin Povišer	3f71bc469d	check: Rephrase comment	2024-07-18 13:08:19 +02:00
Emil J	1166238c0f	Merge pull request #4176 from povik/opt_expr-performance ... Improve `opt_expr` performance	2024-07-15 16:10:25 +02:00
Emil J. Tywoniak	532188f239	opt_expr: change info message	2024-07-15 11:14:47 +02:00
Tony Min	d41688f7d7	Revisions (#4) ... * area should be 1 for all LUTs * clean up macros * add log_assert to fail noisily when encountering oddly configured DFF * clean help msg * flatten set to true by default * update * merge mult tests * remove redundant test * move all dsp tests to single file and remove redundant tests * update ram tests * add more dff tests * fix c++20 compile errors * add option to dump verilog * default to use abc9 * remove -abc9 option since its the default now --------- Co-authored-by: tony <minchunlin@gmail.com>	2024-07-08 10:57:16 -04:00
N. Engelhardt	dac5bd1983	Merge pull request #4455 from phsauter/shiftadd-limit-padding ... peepopt: limit padding from shiftadd	2024-07-06 08:10:25 +02:00
C77874	d0cd01adfe	fixed typos, build with makefile succeeds	2024-07-04 09:33:58 -07:00
C77874	0bb7d1373f	changes made to filenames + references	2024-07-04 08:53:41 -07:00
Chun Lin Min	e5bdc9b5c9	remove DSP48 references	2024-07-03 07:20:29 -07:00
Chun Lin Min	2ced2752e9	replace space indent with tab indent	2024-07-02 13:47:18 -07:00
Chun Lin Min	acddc36389	add PolarFire FPGA support	2024-07-02 12:44:30 -07:00
Catherine	580aaa362d	opt_lut_ins: fix name of global object. NFCI	2024-06-28 15:12:36 +00:00
Emil J. Tywoniak	01f332e750	opt_expr: reduce mostly harmless warning to log	2024-06-25 20:18:49 +02:00
Martin Povišer	fa4a2b6b0d	opt_expr: In clkinv loop ignore irrelevant cells early ... Each call to `handle_clkpol_celltype_swap` has a conversion of the cell's type ID to an allocated string. This can sum up to a non-negligible time being spent in the clkpol code even for a design which doesn't have any flip-flop gates.	2024-06-24 18:32:33 +02:00
Martin Povišer	7a8a69b65c	opt_expr: Revisit sorting in `replace_const_cells` ... Avoid building a cell-to-inbit map when sorting the cells, add a warning if we are unable to sort, and move the code treating non-combinational cells ahead of the rest (this means we don't need to pass non-combinational cells to the TopoSort object at all).	2024-06-24 18:32:33 +02:00
Philippe Sauter	2f0f10cb87	peepopt: limit padding from shiftadd ... The input to a shift operation is padded. This reduced the final number of MUX cells but during techmap it can create huge temporary multiplexers in the log shifter. This significantly increases runtime and resources. A limit is added with a warning when it is used.	2024-06-14 15:33:03 +02:00
Philippe Sauter	74e504330a	peepopt: fix sign check in shiftadd	2024-06-14 13:01:18 +02:00
phsauter	34b5c6d062	peepopt: avoid shift-amount underflow	2024-06-13 23:30:07 +02:00
George Rennie	41aaaa153e	peepopt shiftadd: Only match for sufficiently small constant widths ... This addresses issue #4445	2024-06-12 14:38:12 +01:00
Miodrag Milanovic	9b82a44d25	Fix help message typo	2024-06-07 08:26:59 +02:00
Martin Povišer	4b67f3757f	Merge pull request #4404 from YosysHQ/povik/bbox_derive ... box_derive: New command to derive modules for boxes	2024-05-31 19:09:18 +02:00
Martin Povišer	b230c95cc4	select: Adjust help	2024-05-29 20:41:56 +02:00
Martin Povišer	49906be776	select: Introduce `-assert-mod-count`	2024-05-21 16:34:38 +02:00
Martin Povišer	adc1a01490	select: Refactor some flag validation	2024-05-21 16:29:20 +02:00
Martin Povišer	c0a196173a	Rename `bbox_derive` to `box_derive`	2024-05-21 16:18:03 +02:00
N. Engelhardt	e940d248c0	Merge pull request #4326 from povik/logcmd ... Extend `log` command with `-push`, `-pop`, `-header` options	2024-05-21 15:22:40 +02:00
Martin Povišer	5c929a91c2	bbox_derive: Write help	2024-05-21 14:57:37 +02:00
Martin Povišer	88af059fad	bbox_derive: Fix `done` base type confusion	2024-05-21 14:57:26 +02:00
Emil J. Tywoniak	44b0fdc2bf	bbox_derive: add assert and debug print	2024-05-03 20:43:01 +02:00
Emil J. Tywoniak	e8c58a5528	bbox_derive: fix unininitialized memory UB when run with no named args	2024-05-03 20:41:42 +02:00
Martin Povišer	4c000d3aba	Add new `bbox_derive` command for blackbox derivation	2024-05-03 20:39:11 +02:00
Emil J. Tywoniak	e939182e68	cellmatch: add comments	2024-05-03 16:42:41 +02:00
Martin Povišer	b143e5678f	cellmatch: Rename the special design to `$cellmatch`	2024-05-03 16:42:41 +02:00
Martin Povišer	c0e68dcc4d	cellmatch: Add debug print	2024-05-03 16:42:41 +02:00
Martin Povišer	6a9858cdad	cellmatch: Delegate evaluation to `ConstEval`	2024-05-03 16:42:41 +02:00
Martin Povišer	86e1080f05	cellmatch: New pass	2024-05-03 16:42:41 +02:00
Martin Povišer	6ff4ecb2b4	techmap: Remove `techmap_chtype` from the result	2024-05-03 13:33:28 +02:00
Martin Povišer	fc82251105	techmap: Support dynamic cell types	2024-05-03 13:33:28 +02:00
N. Engelhardt	34d9a7451e	Merge pull request #4333 from YosysHQ/fix_hierarchy_generate ... fix hierarchy -generate mode handling of cells	2024-04-25 09:56:24 +02:00
KrystalDelusion	c3ae33da33	Merge pull request #4285 from YosysHQ/typo_fixup ... Typo fixing	2024-04-25 09:54:48 +12:00
Martin Povišer	171577f909	Merge pull request #4340 from gadfort/abc-lib-merge ... add support for using ABCs library merging when providing multiple liberty files	2024-04-17 22:01:20 +02:00
Jannis Harder	2bd889a59a	formalff -setundef: Fix handling for has_srst FFs ... The `has_srst`` case was checking `sig_ce` instead of `sig_srst` due to a copy and paste error. This would crash when `has_ce` was false and could incorrectly determine that an initial value is unused when `has_ce` and `has_srst` are both set.	2024-04-15 11:53:30 +02:00
Martin Povišer	b827b9862f	Merge pull request #4265 from povik/iattr_help ... memory_map: Explain `-iattr` better	2024-04-13 18:13:58 +02:00
Martin Povišer	4a8cdfabbb	Merge pull request #4169 from povik/clean-opt_clean-step2 ... opt_clean: Remove dead assertion	2024-04-13 18:12:40 +02:00
Peter Gadfort	a48825a604	add support for using ABCs library merging when providing multiple liberty files	2024-04-12 13:57:29 -04:00
N. Engelhardt	b87327d1b9	fix hierarchy -generate mode handling of cells	2024-04-12 13:38:33 +02:00
Emil J	c5912f4f95	Merge pull request #4313 from widlarizer/emil/fix-opt-demorgan-warning ... opt_demorgan: fix extra args warning	2024-04-10 12:49:14 +02:00
Martin Povišer	b00abe4a26	Extend `log` command with `-push`, `-pop`, `-header` options	2024-04-10 11:49:20 +02:00
Martin Povišer	47931f9050	Merge pull request #4295 from gadfort/add-ports-stat ... add port statistics to stat command	2024-04-08 11:12:02 +02:00
Emil J. Tywoniak	4bb3b099d2	opt_demorgan: fix extra args warning	2024-04-03 10:02:53 +02:00
N. Engelhardt	c98cdc2a42	Merge pull request #4184 from povik/check-loop-edges ... Use cell edges data in `check`, improve messages	2024-03-25 16:19:35 +01:00
Peter Gadfort	160e3e089a	add port statistics to stat command	2024-03-22 09:20:20 -04:00
Krystine Sherwin	3eeefd23e3	Typo fixup(s)	2024-03-18 11:09:23 +13:00
N. Engelhardt	e4f11eb0a0	Merge pull request #4228 from povik/synth-inject ... synth: Introduce `-extra-map` for amending techmap	2024-03-11 14:55:45 +01:00
Martin Povišer	206d894c56	check: Omit private wires in loop report	2024-03-11 10:45:36 +01:00
Martin Povišer	d01728aaa5	celledges: Register async FF paths	2024-03-11 10:45:36 +01:00
Martin Povišer	4fdcf388d3	check: Assert edges data is not out-of-bounds	2024-03-11 10:45:17 +01:00
Martin Povišer	b6112b3551	check: Consider read ports in loop detection	2024-03-11 10:45:17 +01:00
Martin Povišer	fa74d0bd1a	check: Use cell edges data in detecting combinational loops	2024-03-11 10:43:49 +01:00
Martin Povišer	c5ae74af34	check: Improve found loop logging ... Print the detected loop in-order, and include source location for each node, if available.	2024-03-11 10:43:49 +01:00
N. Engelhardt	d70113a909	Merge pull request #3972 from nakengelhardt/celledges_shift_ops ... celledges: support shift ops	2024-03-08 09:35:47 +01:00
Martin Povišer	158fbf881e	memory_map: Explain `-iattr` better	2024-03-06 15:15:37 +01:00
Jannis Harder	04ecabdd1f	Merge pull request #4222 from jix/pdr-X ... write_aiger: Include `$assert` and `$assume` cells in -ywmap output	2024-03-05 15:13:51 +01:00
Jannis Harder	d8cdc213a6	rename -witness: Bug fix and rename formal cells ... Rename formal cells in addition to witness signals. This is required to reliably track individual property states for the non-smtbmc flows. Also removes a misplced `break` which resulted in only partial witness renaming.	2024-03-04 16:53:03 +01:00
Jannis Harder	16f6386613	Merge pull request #4224 from povik/equiv_simple-fix ... equiv_simple: Take FFs into account for driver map	2024-03-04 15:53:34 +01:00
N. Engelhardt	6dc5da3ed9	Merge pull request #4232 from povik/mem-ui-fixes ... opt_mem, memory_*: Refuse to operate in presence of processes	2024-02-26 16:09:27 +01:00
Roland Coeurjoly	4a2fb18718	Changes in libs, passes and tests Makefiles. LDLIBS -> LIBS. LDFLAGS -> LINKFLAGS. CXX is clang++ or g++, not clang and gcc	2024-02-25 17:23:56 +01:00
Roland Coeurjoly	033fa10307	We use CXX instead of LD for linking yosys-filterlib	2024-02-25 16:49:28 +01:00
Martin Povišer	030d639201	opt_mem, memory_*: Refuse to operate in presence of processes ... Processes can contain `MemWriteAction` entries which are invisible to most passes operating on memories but which will be lowered to write ports later on by `proc_memwr`. For that reason we can get corrupted RTLIL if we sequence the memory passes before `proc`. Address that by making the affected memory passes ignore modules with processes.	2024-02-23 12:27:53 +01:00
Martin Povišer	975517b022	memory_memx: Fix log header	2024-02-23 12:27:10 +01:00
Martin Povišer	53ca7b48f8	techmap: Fix help message wording	2024-02-22 22:00:56 +01:00
Martin Povišer	4c96546717	equiv_simple: Take FFs into account for driver map ... This fixes an issue introduced in commit 26644ea due to which flip-flops are inadvertently ignored when building up driver map. The mentioned commit wasn't without functional change after all.	2024-02-21 12:05:52 +01:00
Austin Rovinski	03cadf6474	dfflibmap: use patmatch() from kernel/yosys.cc ... Replace OS matching functions with yosys kernel function Signed-off-by: Austin Rovinski <rovinski@nyu.edu>	2024-02-20 11:04:55 -05:00
Miodrag Milanović	bc8a3a5b18	Merge pull request #4219 from rovinski/master ... dfflibmap: Add a -dont_use flag to ignore cells	2024-02-20 12:43:44 +01:00
Miodrag Milanović	a3c81f4d62	Merge pull request #4216 from YosysHQ/show_href ... show: Add option to add cell/wire "src" attribute into graphviz attribute href	2024-02-19 20:50:53 +01:00
Austin Rovinski	5059bb1d4f	dfflibmap: force PathMatchSpecA on WIN32 ... Depending on the WIN32 compilation mode, PathMatchSpec may expect a LPCSTR or LPCWSTR argument. char* is only convertable to LPCSTR, so use that implementation Signed-off-by: Austin Rovinski <rovinski@nyu.edu>	2024-02-19 14:40:46 -05:00
Austin Rovinski	689feed012	dfflibmap: Add a -dont_use flag to ignore cells ... This is an alternative to setting the dont_use property in lib. This brings dfflibmap in parity with the abc pass for dont_use. Signed-off-by: Austin Rovinski <rovinski@nyu.edu>	2024-02-19 13:00:18 -05:00
Martin Povišer	db947e4c71	Merge pull request #4218 from kivikakk/proc_rom-actionless-switch ... proc_rom: don't assert on big actionless switch.	2024-02-19 16:21:40 +01:00
N. Engelhardt	4b99db0b73	Merge pull request #4177 from povik/connect-extra_args ... connect: Do interpret selection arguments	2024-02-19 15:18:37 +01:00
N. Engelhardt	aebb7a0c4d	Merge pull request #4188 from povik/dlatch-bwmux ... proc_dlatch: Include `$bwmux` among considered mux cells	2024-02-19 15:15:03 +01:00
Amelia Cuss	bf4a46ccb3	proc_rom: don't assert on big actionless switch. ... See the test case. PROC_ROM will consider this for evaluation, even though -- without any actions -- lhs is empty (but still "uniform"). A zero-width memory is constructed, which later fails check with: ERROR: Assert `width != 0' failed in kernel/mem.cc:518. Ensure we don't proceed if there's nothing to encode.	2024-02-18 01:33:28 +11:00
N. Engelhardt	61b3b9b58a	Merge pull request #4197 from QuantamHD/sequential_area ... stat: Add sequential area output to stat -liberty	2024-02-16 19:15:44 +01:00
Ethan Mahintorabi	b8a1009de9	Update passes/cmds/stat.cc ... Make reporting line more clear about the non cumulative area of sequential cells Co-authored-by: N. Engelhardt <nakengelhardt@gmail.com>	2024-02-16 07:44:09 -08:00
Ethan Mahintorabi	f0df0e3912	update type and variable names ... Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>	2024-02-16 00:01:44 +00:00
Ethan Mahintorabi	2d8343d423	update type and variable names ... Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>	2024-02-15 23:59:19 +00:00
Jannis Harder	bbdfcfdf30	clk2fflogic: Fix handling of $check cells ... Fixes a bug in the handling of the recently introduced $check cells. Both $check and $print cells in clk2fflogic are handled by the same code and the existing tests for that were only using $print cells. This missed a bug where the additional A signal of $check cells that is not present on $print cells was dropped due to a typo, rendering $check cells non-functional. Also updates the tests to explicitly cover both cell types such that they would have detected the now fixed bug.	2024-02-14 11:42:27 +01:00
Miodrag Milanovic	834276a2f7	show: Add option to add cell/wire "src" attribute into graphviz attribute href	2024-02-14 09:50:53 +01:00
Miodrag Milanović	edb95c69a9	Merge pull request #4084 from jix/scopeinfo ... $scopeinfo support	2024-02-12 09:51:22 +01:00
Ethan Mahintorabi	8566489d85	stat: Add sequential area output to stat -liberty ... Checks to see if a cell is of type ff in the liberty, and keeps track of an additional area value. ``` Chip area for module '\addr': 92.280720 Sequential area for module '\addr': 38.814720 ``` Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>	2024-02-09 23:51:00 +00:00
Miodrag Milanović	2f4c917dac	Merge pull request #4181 from povik/ci-cxxstd-fix ... ci: Fix CXXSTD typo	2024-02-08 18:55:47 +01:00
Martin Povišer	043f1e2bcb	opt_lut: Remove leftover `-dlogic` help	2024-02-08 17:49:44 +01:00
Martin Povišer	af1a5cfeb9	Address `SigBit`/`SigSpec` confusion issues under c++20	2024-02-08 17:48:36 +01:00
Martin Povišer	862f2fd705	proc_dlatch: Include `$bwmux` among considered mux cells	2024-02-08 00:08:50 +01:00
Jannis Harder	bfd9cf63db	Ignore $scopeinfo in opt_merge	2024-02-06 17:51:29 +01:00
Jannis Harder	8902fc94b6	Suport $scopeinfo in flatten and opt_clean	2024-02-06 17:51:29 +01:00
Miodrag Milanović	269c50f90e	Merge pull request #4130 from jix/hierarchy-defer-notop ... hierarchy: Without a known top module, derive all deferred modules	2024-02-06 12:08:01 +01:00
Jannis Harder	0470cbb00d	hierarchy: Without a known top module, derive all deferred modules ... This fixes hierarchy when used with cell libraries that were loaded with -defer and also makes more of the hierarchy visible to the auto-top heuristic.	2024-02-06 10:31:40 +01:00
Claire Xen	1b73b5beb7	Merge pull request #4174 from YosysHQ/claire/overwrite ... Add API to overwrite existing pass from plugin	2024-02-05 23:49:24 +01:00
N. Engelhardt	f96e27ac14	Merge pull request #4123 from povik/clean-opt_clean ... opt_clean: Add commentary, remove dead code	2024-02-05 15:08:34 +01:00
Catherine	c7bf0e3b8f	Add new `$check` cell to represent assertions with a message.	2024-02-01 20:10:39 +01:00
Jannis Harder	e1a59ba80b	async2sync, clk2fflogic: Add support for $check and $print cells	2024-02-01 20:10:39 +01:00
Jannis Harder	6c4902313b	chformal: Support $check cells and add chformal -lower ... This adds support for `$check` cells in chformal and adds a `-lower` mode which converts `$check` cells into `$assert` etc. cells with a `$print` cell to output the `$check` message.	2024-02-01 20:10:39 +01:00
Martin Povišer	a84fa0a277	connect: Do interpret selection arguments ... Instead of silently ignoring what would ordinarily be the selection arguments to a pass, interpret those and mark the support in the help message.	2024-02-01 10:28:36 +01:00
Martin Povišer	6c4bc5aae5	Merge pull request #4165 from phsauter/shiftadd-offset-fix ... peepopt: handle offset too large in `shiftadd`	2024-01-31 13:47:39 +01:00
Philippe Sauter	cbdf9b2f9c	peepopt: handle empty src-attribute in shiftadd	2024-01-31 13:07:01 +01:00
Claire Xenia Wolf	4fa314c0bd	Add API to overwrite existing pass from plugin ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-01-30 17:51:11 +01:00
Philippe Sauter	7f8b6dd982	peepopt: delete unnecessary comment in shiftadd	2024-01-30 09:51:21 +01:00
Martin Povišer	23c9828d70	opt_clean: Remove dead branch	2024-01-29 11:26:44 +01:00
Martin Povišer	7afc0696e2	opt_clean: Assert an impossible path isn't taken	2024-01-29 11:26:44 +01:00
Martin Povišer	ec065186d3	opt_clean: Add commentary around wire cleaning, NFC	2024-01-29 11:26:44 +01:00
Philippe Sauter	68a9aa7c29	peepopt: handle offset too large in `shiftadd` ... If the offset is larger than the signal itself, meaning the signal is completely shifted out, it tried to extract a negative amount of bits from the old signal. This RTL pattern is suspicious since it is a complicated way of arriving at a constant value, so we warn the user.	2024-01-26 16:44:30 +01:00
Jannis Harder	7c818d30f7	sim: Bring $print trigger/sampling semantics in line with FFs	2024-01-25 16:21:03 +01:00
Catherine	3d9e44d182	hierarchy: keep display statements, like formal assertions.	2024-01-22 10:09:22 +00:00
Stephen Tong	b3e7390c0e	Fix typo in stat help	2024-01-21 16:32:05 -05:00
N. Engelhardt	e1f4c5c9cb	Merge pull request #4133 from YosysHQ/show_color_proc ... show: allow setting colors via selection on PROC boxes	2024-01-17 17:56:53 +01:00
Martin Povišer	6a7fad4dd9	Merge pull request #4132 from povik/opt_lut_ice40 ... opt_lut: Replace `-dlogic` with `-tech ice40`	2024-01-17 14:26:28 +01:00
N. Engelhardt	fb4eeb1344	show: allow setting colors via selection on PROC boxes	2024-01-15 17:47:59 +01:00
Martin Povišer	149bcd88ad	Merge pull request #4026 from uis246/fix-format ... Fix printf formats	2024-01-15 16:04:11 +01:00
Martin Povišer	568418b50b	opt_lut: Replace `-dlogic` with `-tech ice40`	2024-01-15 12:35:21 +01:00
uis	5902b2826d	Fix printf formats	2024-01-15 12:07:54 +01:00
Dag Lem	acf916f654	Restore sim output from initial $display	2024-01-14 16:52:51 +01:00
Jannis Harder	57b4e16acd	sim: Include $display output in JSON summary ... This allows tools like SBY to capture the $display output independent from anything else sim might log. Additionally it provides source and hierarchy locations for everything printed.	2024-01-11 12:01:39 +01:00
N. Engelhardt	78541be4d8	Merge pull request #3971 from povik/equiv_simple-fixes ... Fixes to `equiv_simple`	2023-12-18 16:31:02 +01:00
Jannis Harder	cca12d9d9b	Merge pull request #4055 from povik/sim-hier-prints ... sim: Print hierarchy for failed assertions	2023-12-11 16:55:36 +01:00
Jannis Harder	7b74caa5db	peepopt: Fix padding for the peepopt_shiftmul_right pattern ... The previous version could easily generate a large amount of padding when the constant factor was significantly larger than the width of the shift data input. This could lead to huge amounts of logic being generated before then being optimized away at a huge performance and memory cost. Additionally and more critically, when the input width was not a multiple of the constant factor, the input data was padded with 'x bits to such a multiple before interspersing the 'x padding needed to align the selectable windows to power-of-two offsets. Such a final padding would not be correct for shifts besides $shiftx, and the previous version did attempt to remove that final padding at the end so that the native zero/sign/x-extension behavior of the shift cell would be used, but since the last selectable window also got power-of-two padding appended after the padding the code is trying to remove got added, it did not actually fully remove it in some cases. I changed the code to only add 'x padding between selectable windows, leaving the last selectable window unpadded. This omits the need to add final padding to a multiple of the constant factor in the first place. In turn, that means the only 'x bits added are actually impossible to select. As a side effect no padding is added when the constant factor is equal to or larger than the width of the shift data input, also solving the reported performance bug. This fixes #4056	2023-12-06 18:35:44 +01:00
Martin Povišer	6581b5593c	sim: Print hierarchy for failed assertions	2023-12-06 12:09:07 +01:00
Martin Povišer	16ea497d7c	pmgen: Have a single make pattern ... Remove duplicate %.pmg -> %_pm.h pattern. One of the duplicates overrode the other, and in some conditions there were build races as to whether the target directory for the generated header would exist. Instead have a single rule which is properly generalized.	2023-12-05 18:30:13 +01:00
Martin Povišer	d6566eb344	booth: Redo baseline architecture summation ... Redo the summation logic: strive for some degree of balance on the generated Wallace tree, emit an `$add` cell for the final summation.	2023-11-22 15:47:11 +01:00
Martin Povišer	beb5cb55a5	booth: Expose `-lowpower` option	2023-11-22 15:29:59 +01:00
Martin Povišer	7005ea9411	booth: Revisit help	2023-11-22 15:29:59 +01:00
Martin Povišer	48b73be8c6	booth: Replace the default signed architecture ... Generalize what was formerly the unsigned-only architecture to support both signed and unsigned multiplication, use that as default, and set aside the special low-power architecture that was formerly used for signed multipliers.	2023-11-22 15:29:59 +01:00
Martin Povišer	f50894d8bf	booth: Drop extra decoder arguments	2023-11-22 15:29:54 +01:00
Martin Povišer	579f6bdc17	booth: Do not special-case bottom rows ... Later on all the rows are cropped to the target size anyway, so there's no harm in transitionally including extra top bits.	2023-11-22 15:12:15 +01:00
Martin Povišer	da207cdce0	booth: Make less assumptions when aligning partial products	2023-11-22 15:12:15 +01:00
Martin Povišer	69e994ff75	booth: Clean unused FA index variable	2023-11-22 12:47:09 +01:00
Martin Povišer	d8408b2350	booth: Move up signed quadrant 1 logic	2023-11-22 12:46:15 +01:00
Martin Povišer	8d33cc2fb6	booth: Refactor signed CPA	2023-11-22 12:46:15 +01:00
Martin Povišer	00e899f98d	booth: Refactor signed multiplier full adders emission	2023-11-22 12:46:15 +01:00
N. Engelhardt	63cec22a0c	Merge pull request #3883 from phsauter/peepopt-shiftadd ... peepopt: Add `shiftadd` pattern	2023-11-07 10:42:15 +01:00
phsauter	3618294bac	peepopt: Add assert of consistent `shiftadd` data	2023-11-06 16:35:00 +01:00