Commit Graph

18230 Commits

Author SHA1 Message Date
Akash Levy ba09c6c173 Better reduce_* message 2025-02-18 04:34:54 -08:00
Akash Levy ef9645990e Reduce pass verbosity 2025-02-18 04:05:40 -08:00
Krystine Sherwin dc03e174af
fixup! Makefile: Warn if submodule status '+'-prefixed 2025-02-18 11:46:11 +13:00
Krystine Sherwin 03d9138744
Makefile: 'U'-prefixed submodule status
Covering all the bases, I guess?  '-'-prefix is already correctly handled by the base case message.
If the user somehow gets merge conflicts in abc, hopefully they know what they're doing.
2025-02-18 11:33:06 +13:00
Krystine Sherwin b8777d7893
Makefile: Warn if submodule status '+'-prefixed
A '+'-prefix means that the submodule is initialized and checked out, but a different commit is checked out.
If this is accidental then the user should run `git submodule update` to fix it.
If it is intentional (because e.g. the user is explicitly wanting to test Yosys with a different version of abc), then creating a new commit in Yosys to update the expected commit is also a valid solution.
2025-02-18 11:25:04 +13:00
Emil J. Tywoniak 2b33937ab8 liberty: fix clear and preset latches 2025-02-17 17:36:51 +01:00
Akash Levy 33c72b0f25
Merge branch 'YosysHQ:main' into main 2025-02-15 15:54:28 -08:00
Akash Levy d0016fed75 Smallfix 2025-02-14 16:44:43 -08:00
Akash Levy 8083d9b9da
Fix share copy 2025-02-14 16:43:58 -08:00
github-actions[bot] 38f858374c Bump version 2025-02-15 00:20:50 +00:00
KrystalDelusion 508e7327e4
Merge pull request #4899 from YosysHQ/shr_int_max
Fix runtime error on shift by INT_MAX
2025-02-15 09:52:33 +13:00
Akash Levy f01bcddd9e Need wreduce in SMALL mode 2025-02-14 12:25:18 -08:00
Akash Levy 9397847959 Reenable UPF stuff for now 2025-02-14 12:21:43 -08:00
Emil J. Tywoniak 8968986b54 share: add -pattern-limit to set analysis effort on branch-unbranch mux regions 2025-02-14 21:13:07 +01:00
Akash Levy e5617883e1 Revert some stuff 2025-02-14 11:57:20 -08:00
Akash Levy 3bca4c10d8 Fix macOS boost-python issues 2025-02-14 11:43:00 -08:00
Akash Levy 3676429634 `aldff`s do not get split by splitcells 2025-02-14 10:53:51 -08:00
Akash Levy cf65cb2cf1 Copy abc stuff for pyosys 2025-02-14 10:41:16 -08:00
Akash Levy fb24decc64 Smallfixes 2025-02-14 10:38:19 -08:00
Akash Levy 7cc06ebaab Small fixes 2025-02-14 10:34:27 -08:00
Akash Levy c4254a9a95 Final cleanup 2025-02-14 10:18:13 -08:00
Akash Levy 1b13b5d6ea Move segv and reenable loops.v test 2025-02-14 10:02:30 -08:00
Akash Levy fd811ddaee Cleanup 2025-02-14 08:48:27 -08:00
Akash Levy f76fd9280b Clean up Verific 2025-02-14 06:56:20 -08:00
Akash Levy db83aaee09 Clean up muxpack 2025-02-14 06:56:12 -08:00
Akash Levy 0f5f9ae28c Small refactor 2025-02-14 04:40:51 -08:00
Akash Levy cddfd1f12a Formatting 2025-02-14 04:26:26 -08:00
Akash Levy 8369792e03 Improve extract_reduce further 2025-02-13 21:40:04 -08:00
Akash Levy 9cc82c7044 Revert clocking.ys 2025-02-13 20:32:17 -08:00
Akash Levy 500997fec9 Ignore err and log files 2025-02-13 19:40:40 -08:00
Akash Levy c8c97ea00b Revert back to using Verific naming 2025-02-13 19:40:33 -08:00
Akash Levy aa515e8847 Bump backward-cpp dep 2025-02-13 17:47:01 -08:00
Akash Levy 78d05ddfc8
Merge pull request #52 from alaindargelas/longloop_support_cache
longloop honors caching
2025-02-13 17:28:02 -08:00
Krystine Sherwin 4c728968a3
Fix runtime error on shr INT_MAX 2025-02-14 14:01:36 +13:00
Krystine Sherwin db5b76edc1
Add test for shifting by INT_MAX
Currently resulting in CI failing on main during fsm checks which generate a circuit that simplifies to this.
2025-02-14 14:01:27 +13:00
Alain Dargelas 077b4b854c longloop honors caching 2025-02-13 15:49:18 -08:00
Anhijkt a8052f653a write_xaiger: Detect and error on combinatorial loops 2025-02-14 01:21:39 +02:00
Akash Levy 7d33fd463b Add is_mostly_const to SigSpec 2025-02-13 11:11:33 -08:00
Akash Levy 610d4cc716 Allow extract_reduce to operate on xnors and single-bit word-wide operators 2025-02-12 15:57:28 -08:00
Akash Levy cefce37e59
Merge branch 'YosysHQ:main' into main 2025-02-12 09:01:46 -08:00
Emil J df3c62a4ed
Merge pull request #4892 from YosysHQ/emil/fix-memory-libmap-dangling-cells
memory_libmap: update indices on design modification
2025-02-12 10:21:01 +01:00
Emil J. Tywoniak 01d2bfcf00 share: fix infinite loop in find_terminal_bits on $mux loop 2025-02-12 10:16:44 +01:00
github-actions[bot] 359901a964 Bump version 2025-02-12 00:21:01 +00:00
Emil J. Tywoniak 55b60dca95 memory_libmap: update indices on design modification 2025-02-11 13:32:34 +01:00
Miodrag Milanovic 6f9c515a22 Next dev cycle 2025-02-11 08:40:50 +01:00
Miodrag Milanovic b5170e1394 Release version 0.50 2025-02-11 07:55:17 +01:00
Akash Levy 360a03da1d Yosys smallfix bump dep 2025-02-10 18:09:16 -08:00
github-actions[bot] ce5ad2a554 Bump version 2025-02-11 00:20:46 +00:00
KrystalDelusion 78f27e174f
Merge pull request #4887 from JasonBrave/remove-makefile-clean-docs-images-target
Remove obsolete Makefile docs/images clean call
2025-02-11 10:31:59 +13:00
Jason Xu 333588265c Remove obsolete Makefile docs/images clean call 2025-02-09 10:22:35 -05:00