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2086 Commits

Author SHA1 Message Date
Akash Levy e50a5974f7 Get rid of SYNTHESIS redefinition warning 2025-05-28 08:33:56 +02:00
Akash Levy 3fc74be3e2
Merge branch 'YosysHQ:main' into main 2025-05-28 01:54:49 +02:00
KrystalDelusion 489a12d6c1
Merge pull request #5141 from garytwong/unique-if 
Accept (and ignore) SystemVerilog unique/priority if.
 2025-05-27 09:45:50 +12:00
Akash Levy 3a23e772dd
Merge branch 'YosysHQ:main' into main 2025-05-24 12:11:52 -07:00
Emil J 4b8d42d22c
Merge pull request #5095 from YosysHQ/emil/one-bit-width 
rtlil: enable single-bit vector wires
 2025-05-23 15:55:45 +02:00
Gary Wong 9770ece187 Accept (and ignore) SystemVerilog unique/priority if. 
Add support to the "read_verilog -sv" parser to validate the
"unique", "unique0", and "priority" keywords in contexts where
they're legal according to 1800-2012 12.4.2.

This affects only the grammar accepted; the behaviour of conditionals
is not changed.  (But accepting this syntax will provide scope for
possible optimisations as future work.)

Three test cases ("unique_if", "unique_if_else", and
"unique_if_else_begin") verify that the keywords are accepted where
legal and rejected where illegal, as described in the final paragraph
of 12.4.2.
 2025-05-22 19:28:28 -06:00
Akash Levy ccc2ba41f2
Merge branch 'YosysHQ:main' into main 2025-05-12 15:02:55 -07:00
Emil J. Tywoniak e5171d6aa1 verific: support single_bit_vector 2025-05-12 13:23:29 +02:00
Emil J. Tywoniak 5e72464a15 rtlil: enable single-bit vector wires 2025-05-12 13:23:29 +02:00
Krystine Sherwin fe0abb7026
simplify.cc: Fix mem leak 2025-05-10 17:10:47 +12:00
Akash Levy 3bcbfe4dde verific -set_relaxed_file_libext_modes 2025-05-08 23:43:23 -07:00
Akash Levy f3d24aea76 Add spaces in verific 2025-05-08 22:24:10 -07:00
Akash Levy 380850321d Refactor verific -optimization and -no_split_complex_ports into verific pass 2025-05-08 15:59:47 -07:00
Akash Levy 7191be492c
Merge branch 'YosysHQ:main' into main 2025-05-05 15:36:40 -07:00
Krystine Sherwin 23cb007068
verilog_parser.y: Delete unused TOK_ID 
Fixes memory leak when parameter has no value.
 2025-05-05 10:04:13 +12:00
Akash Levy 618cf9d372
Merge branch 'YosysHQ:main' into main 2025-04-28 13:57:29 -07:00
N. Engelhardt 8bdbf797d0
Merge pull request #5017 from YosysHQ/micko/ram_blasting 2025-04-28 13:33:48 +00:00
Akash Levy 94bc6937d3
Merge branch 'YosysHQ:main' into main 2025-04-27 15:24:30 -07:00
Emil J. Tywoniak bdc2597f79 simplify: fix struct wiretype attr memory leak 2025-04-25 01:00:08 +02:00
Miodrag Milanovic 22e6ce4282 verific: bit blast RAM if using mem2reg attribute 2025-04-14 15:24:11 +02:00
Akash Levy 3e24a3e248 Bump yosys to latest 2025-04-08 18:05:28 -07:00
Miodrag Milanovic 406ee4c8d3 read_verilog_file_list: change short help message to start with lower case 2025-04-08 13:20:16 +02:00
Akash Levy 06c614a010
Merge branch 'YosysHQ:main' into main 2025-04-07 07:28:06 -07:00
Akash Levy 61715c2c28 Fix memory too large issue 2025-04-04 03:22:22 -07:00
Akash Levy f218b5ba58 Revert "Represent memory size with size_t" 
This reverts commit bb5f8415af.
 2025-04-04 03:20:07 -07:00
Akash Levy bb5f8415af Represent memory size with size_t 2025-04-04 02:04:34 -07:00
Jannis Harder 0f13b55173 Liberty file caching with new `libcache` command 
This adds optional in-memory caching of parsed liberty files to speed up
flows that repeatedly parse the same liberty files. To avoid increasing
the memory overhead by default, the caching is disabled by default. The
caching can be controlled globally or on a per path basis using the new
`libcache` command, which also allows purging cached data.
 2025-04-03 13:39:35 +02:00
Akash Levy 4bd08ac362
Merge branch 'YosysHQ:main' into main 2025-04-01 22:10:43 -07:00
Miodrag Milanovic 72f2185a94 verific: fix restoring msg state after blackbox import 2025-04-01 17:35:59 +02:00
Akash Levy d2028feefe Set Verific flags via -cfg instead of in Yosys 2025-03-25 22:41:06 -07:00
Akash Levy 95f489beec Merge nice gzip refactor 2025-03-20 16:47:12 -07:00
Emil J. Tywoniak 813f909460 gzip: istream 2025-03-19 13:43:44 +01:00
Emil J. Tywoniak 4f3fdc8457 io: refactor string and file work into new unit 2025-03-19 13:43:42 +01:00
Alain Dargelas 3021dab37d memory limit fix and increased limit 2025-03-17 09:07:33 -07:00
Akash Levy bc3ca6210c Add back operator optimization for Verific frontend 2025-03-17 04:06:28 -07:00
Akash Levy 1c0d4a43b3
Merge branch 'YosysHQ:main' into main 2025-03-14 18:07:55 -07:00
Alain Dargelas 88211310fa code review 2025-03-12 16:32:42 -07:00
Alain Dargelas dcce15207e Memory size check 2025-03-12 16:21:18 -07:00
Jason Xu a5f34d04f8 Address comments 2025-03-11 18:50:44 -04:00
Jason Xu 98eefc5d1a Add file list support to read pass 2025-03-07 20:44:21 -05:00
Jason Xu bf1eab565b Fix compile on WASI platform 2025-03-07 20:20:27 -05:00
Jason Xu ac31bad656 Address all comments 2025-03-07 20:16:28 -05:00
Jason Xu 8ec96ec806 Address most comments 2025-03-07 20:16:28 -05:00
Jason Xu 0678c4dec9 Coding style update 2025-03-07 20:16:28 -05:00
Jason Xu f62a9be153 Initial file list support 2025-03-07 20:16:28 -05:00
Akash Levy 881080a827 Merge upstream 2025-03-05 07:54:26 -08:00
Emil J 39aacc95df
Merge pull request #4907 from YosysHQ/emil/fix-clear-preset-latch 
liberty: fix clear and preset latches
 2025-03-03 18:53:12 +01:00
Akash Levy 9d3b7f7474
Merge branch 'YosysHQ:main' into main 2025-02-26 09:51:44 -08:00
Martin Povišer 732ed67014 ast/dpicall: Stop using variable length array 
Fix the compiler warning

    variable length arrays in C++ are a Clang extension [-Wvla-cxx-extension]
 2025-02-24 17:32:30 +01:00
Emil J. Tywoniak 2b33937ab8 liberty: fix clear and preset latches 2025-02-17 17:36:51 +01:00