14 Commits

Author	SHA1	Message	Date
Eddie Hung	0597a3ea23	Rename to XilinxDspPass	2019-08-13 10:23:07 -07:00
Eddie Hung	0b5b56c1ec	Pack partial-product adder DSP48E1 packing	2019-08-09 15:19:33 -07:00
Eddie Hung	747690a6df	Remove muxY and ffY for now	2019-08-08 16:33:37 -07:00
Eddie Hung	911129e3ef	Disable $dffe	2019-08-08 10:44:49 -07:00
Eddie Hung	ed7540a46f	Pack P register properly	2019-08-01 15:10:43 -07:00
Eddie Hung	9ad11ea2cc	Fine tune ice40_dsp.pmg, add support for packing subsets of registers	2019-07-19 10:57:32 -07:00
Eddie Hung	90ac147eb2	Do not autoremove ffP aor muxP	2019-07-18 15:02:41 -07:00
Eddie Hung	08fe63c61e	Improve pattern matcher to match subsets of $dffe? cells	2019-07-18 14:08:18 -07:00
Eddie Hung	79d63479ea	Improve A/B reg packing	2019-07-18 13:30:35 -07:00
Eddie Hung	e075f0dda0	Do not autoremove A/B registers since they might have other consumers	2019-07-18 13:22:22 -07:00
Eddie Hung	91629ee4b3	Pattern matcher to check pool of bits, not exactly	2019-07-17 12:45:25 -07:00
Eddie Hung	3f677fb0db	Signed extension	2019-07-16 15:54:07 -07:00
Eddie Hung	9616dbd125	Add support {A,B,P}REG packing	2019-07-16 14:06:32 -07:00
Eddie Hung	dd59375a66	Add xilinx_dsp for register packing	2019-07-15 14:46:31 -07:00