From fd41f9fa7ce0fad6cbc6c8be3d20f24bd2855b1a Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 30 Sep 2026 15:57:44 +0200
Subject: [PATCH] techlibs: ignore problematic block for verific, we anyway
 load as blackbox only

---
 techlibs/xilinx/cells_sim.v | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 8b0c913aa..62edff3c8 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -3456,7 +3456,7 @@ module DSP48E1 (
         if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE")      \D.PCOUT.comb = 3700;
     end
     endfunction
-
+`ifndef VERIFIC
     generate
         if (PREG == 0 && MREG == 0 && AREG == 0 && ADREG == 0)
             specify
@@ -3521,6 +3521,7 @@ module DSP48E1 (
                 if ( IS_CLK_INVERTED && CEP) (negedge CLK => (PCOUT : 48'bx)) = \PCOUT.arrival () ;
             endspecify
     endgenerate
+`endif
 `endif
 
     initial begin