diff --git a/docs/source/code_examples/macro_commands/prep.ys b/docs/source/code_examples/macro_commands/prep.ys
index 7ec7c7af8..1bec907f6 100644
--- a/docs/source/code_examples/macro_commands/prep.ys
+++ b/docs/source/code_examples/macro_commands/prep.ys
@@ -17,7 +17,6 @@ coarse:
     opt_clean
     memory_collect
     opt -noff -keepdc -fast
-    sort
 
 check:
     stat
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 04418c45b..d27eabc25 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -2992,8 +2992,6 @@ void RTLIL::Module::add(RTLIL::Binding *binding)
 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
 {
 	log_assert(refcount_wires_ == 0);
-	if (wires.empty())
-		return;
 
 	struct DeleteWireWorker
 	{
diff --git a/passes/opt/opt.cc b/passes/opt/opt.cc
index 983437e64..ec5760cd9 100644
--- a/passes/opt/opt.cc
+++ b/passes/opt/opt.cc
@@ -193,6 +193,7 @@ struct OptPass : public Pass {
 		}
 
 		design->optimize();
+		design->sort();
 		design->check();
 
 		log_header(design, "Finished fast OPT passes.%s\n", fast_mode ? "" : " (There is nothing left to do.)");
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index bd244d62b..237d6cf0d 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -271,9 +271,6 @@ bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool &regs, SigPoo
 			return conns.check_any(s2);
 	}
 
-	if (w1 == w2)
-		return s2.offset < s1.offset;
-
 	if (w1->port_output != w2->port_output)
 		return w2->port_output;
 
@@ -346,7 +343,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool unused
 		RTLIL::Wire *wire = it.second;
 		for (int i = 0; i < wire->width; i++) {
 			RTLIL::SigBit s1 = RTLIL::SigBit(wire, i), s2 = assign_map(s1);
-			if (compare_signals(s2, s1, register_signals, connected_signals, direct_wires))
+			if (!compare_signals(s1, s2, register_signals, connected_signals, direct_wires))
 				assign_map.add(s1);
 		}
 	}
@@ -724,6 +721,7 @@ struct OptCleanPass : public Pass {
 			log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires);
 
 		design->optimize();
+		design->sort();
 		design->check();
 
 		keep_cache.reset();
@@ -788,6 +786,7 @@ struct CleanPass : public Pass {
 			log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires);
 
 		design->optimize();
+		design->sort();
 		design->check();
 
 		keep_cache.reset();
diff --git a/techlibs/common/prep.cc b/techlibs/common/prep.cc
index 6798f2a5d..a98619abd 100644
--- a/techlibs/common/prep.cc
+++ b/techlibs/common/prep.cc
@@ -211,7 +211,6 @@ struct PrepPass : public ScriptPass
 				run("memory_collect");
 			}
 			run(nokeepdc ? "opt -noff -fast" : "opt -noff -keepdc -fast");
-			run("sort");
 		}
 
 		if (check_label("check"))
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index 36d827b7c..b9902659c 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -311,7 +311,6 @@ struct SynthGowinPass : public ScriptPass
 
 		if (check_label("map_luts"))
 		{
-			run("sort");
 			if (nowidelut && abc9) {
 				run("read_verilog -icells -lib -specify +/abc9_model.v");
 				run("abc9 -maxlut 4 -W 500");
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index c487206db..46b30573c 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -386,8 +386,6 @@ struct SynthXilinxPass : public ScriptPass
 				run("pmux2shiftx", "(skip if '-nosrl' and '-widemux=0')");
 				run("clean", "      (skip if '-nosrl' and '-widemux=0')");
 			}
-
-			run("sort");
 		}
 
 		if (check_label("map_dsp", "(skip if '-nodsp')")) {