diff --git a/kernel/fstdata.cc b/kernel/fstdata.cc index 899447773..2e3c429a5 100644 --- a/kernel/fstdata.cc +++ b/kernel/fstdata.cc @@ -397,40 +397,11 @@ int FstData::getWidth(fstHandle signal) } // Auto-discover scope from FST by finding the top module -std::string FstData::autoScope(Module *topmod) { +std::string FstData::autoScope(Module *topmod) { - log("Auto-discovering scope from file...\n"); + log("Auto-discovering scopes from %d candidates...\n", GetSize(name_to_handle)); std::string top = RTLIL::unescape_id(topmod->name); - - log("Available scopes:\n"); - std::set unique_scopes; - for (const auto& var : vars) { - unique_scopes.insert(var.scope); - } - for (const auto& scope : unique_scopes) { - log(" %s\n", scope.c_str()); - } - - // Option 1 - Instance based scope matching - // Will fail if the DUT instance name != the top module name - log("Trying instance-based scope matching...\n"); - for (const auto& var : vars) { - // Check if this scope ends with our top module - log_debug("Checking scope: %s\n", var.scope.c_str()); - if (var.scope == top || - var.scope.find("." + top) != std::string::npos) { - // Extract the full path up to (and including) the top module - size_t pos = var.scope.find(top); - if (pos != std::string::npos) { - std::string scope = var.scope.substr(0, pos + top.length()); - return scope; - } - } - } - - // Option 2 - Port based scope matching - // Matches based on exact port name matching of the top module - log("Trying port-based scope matching...\n"); + std::string scope = ""; // Map top module port name to their bit widths (RTL reference point) dict top2widths; @@ -439,7 +410,7 @@ std::string FstData::autoScope(Module *topmod) { top2widths[RTLIL::unescape_id(wire->name)] = wire->width; } } - log("Extracted %d ports from top module\n", GetSize(top2widths)); + log("Extracted %d ports from module '%s'\n", GetSize(top2widths), top.c_str()); // For each scope, track the number of matching ports dict scopes2matches; @@ -456,7 +427,7 @@ std::string FstData::autoScope(Module *topmod) { if (last_dot != std::string::npos) { // no '.' means no scope/signal extraction is possible std::string scope = name.substr(0, last_dot); std::string signal_name = name.substr(last_dot + 1); - + // Check that signal is in the top module and width matches if (top2widths.count(signal_name)) { int signal_width = getWidth(handle); @@ -467,24 +438,28 @@ std::string FstData::autoScope(Module *topmod) { } } - // Find scopes with exact matches - // If there is a tie, return the longest scope - std::string result = ""; + // Find scopes with exact matches and add to array + std::vector results; for (const auto& entry : scopes2matches) { int num_matches = entry.second; if (num_matches == GetSize(top2widths)) { std::string scope = entry.first; - if (result.empty() || scope.length() > result.length()) { - result = scope; - } + results.push_back(scope); } } - if (!result.empty()) { - return result; + if (results.empty()) { + log_warning("Could not auto-discover scope for module '%s'...\n", + top.c_str()); + return ""; + } else { + log("Found %d scopes for module '%s':\n", GetSize(results), top.c_str()); + for (const auto& scope : results) { + log(" %s\n", scope.c_str()); + } + if (results.size() > 1) { + log_warning("Multiple scopes found for module '%s'. Using the first one.\n", + top.c_str()); + } + return results[0]; } - - // No match found - log_warning("Could not auto-discover scope for module '%s'...\n", - RTLIL::unescape_id(topmod->name).c_str()); - return ""; } diff --git a/kernel/mem.cc b/kernel/mem.cc index 02d12dea4..f16f2082d 100644 --- a/kernel/mem.cc +++ b/kernel/mem.cc @@ -753,6 +753,40 @@ namespace { int n_wr_ports = cell->parameters.at(ID::WR_PORTS).as_int(); Const rd_wide_continuation = is_compat ? Const(State::S0, n_rd_ports) : cell->parameters.at(ID::RD_WIDE_CONTINUATION); Const wr_wide_continuation = is_compat ? Const(State::S0, n_wr_ports) : cell->parameters.at(ID::WR_WIDE_CONTINUATION); + pool bad_params; + if (!is_compat) { + auto check_param_size = [&](IdString param_name, int expected_size) { + const Const ¶m = cell->parameters.at(param_name); + if (GetSize(param) != expected_size) { + log_warning("Memory cell %s.%s (%s) has inconsistent parameter %s: expected size %d, got %d\n", + log_id(cell->module), log_id(cell), log_id(res.memid), + log_id(param_name), expected_size, GetSize(param)); + bad_params.insert(param_name); + } + }; + check_param_size(ID::RD_WIDE_CONTINUATION, n_rd_ports); + check_param_size(ID::RD_CLK_ENABLE, n_rd_ports); + check_param_size(ID::RD_CLK_POLARITY, n_rd_ports); + check_param_size(ID::RD_CE_OVER_SRST, n_rd_ports); + check_param_size(ID::RD_ARST_VALUE, n_rd_ports * res.width); + check_param_size(ID::RD_SRST_VALUE, n_rd_ports * res.width); + check_param_size(ID::RD_INIT_VALUE, n_rd_ports * res.width); + check_param_size(ID::RD_TRANSPARENCY_MASK, n_rd_ports * n_wr_ports); + check_param_size(ID::RD_COLLISION_X_MASK, n_rd_ports * n_wr_ports); + check_param_size(ID::WR_WIDE_CONTINUATION, n_wr_ports); + check_param_size(ID::WR_CLK_ENABLE, n_wr_ports); + check_param_size(ID::WR_CLK_POLARITY, n_wr_ports); + check_param_size(ID::WR_PRIORITY_MASK, n_wr_ports * n_wr_ports); + if (bad_params.count(ID::RD_WIDE_CONTINUATION)) + rd_wide_continuation = Const(State::S0, n_rd_ports); + if (bad_params.count(ID::WR_WIDE_CONTINUATION)) + wr_wide_continuation = Const(State::S0, n_wr_ports); + } + auto safe_param_extract = [&](IdString param_name, int offset, int len) -> Const { + if (bad_params.count(param_name)) + return Const(State::S0, len); + return cell->parameters.at(param_name).extract(offset, len); + }; for (int i = 0, ni; i < n_rd_ports; i = ni) { ni = i + 1; while (ni < n_rd_ports && rd_wide_continuation[ni] == State::S1) @@ -760,8 +794,8 @@ namespace { MemRd mrd; mrd.wide_log2 = ceil_log2(ni - i); log_assert(ni - i == (1 << mrd.wide_log2)); - mrd.clk_enable = cell->parameters.at(ID::RD_CLK_ENABLE).extract(i, 1).as_bool(); - mrd.clk_polarity = cell->parameters.at(ID::RD_CLK_POLARITY).extract(i, 1).as_bool(); + mrd.clk_enable = safe_param_extract(ID::RD_CLK_ENABLE, i, 1).as_bool(); + mrd.clk_polarity = safe_param_extract(ID::RD_CLK_POLARITY, i, 1).as_bool(); mrd.clk = cell->getPort(ID::RD_CLK).extract(i, 1); mrd.en = cell->getPort(ID::RD_EN).extract(i, 1); mrd.addr = cell->getPort(ID::RD_ADDR).extract(i * abits, abits); @@ -774,16 +808,16 @@ namespace { mrd.arst = State::S0; mrd.srst = State::S0; } else { - mrd.ce_over_srst = cell->parameters.at(ID::RD_CE_OVER_SRST).extract(i, 1).as_bool(); - mrd.arst_value = cell->parameters.at(ID::RD_ARST_VALUE).extract(i * res.width, (ni - i) * res.width); - mrd.srst_value = cell->parameters.at(ID::RD_SRST_VALUE).extract(i * res.width, (ni - i) * res.width); - mrd.init_value = cell->parameters.at(ID::RD_INIT_VALUE).extract(i * res.width, (ni - i) * res.width); + mrd.ce_over_srst = safe_param_extract(ID::RD_CE_OVER_SRST, i, 1).as_bool(); + mrd.arst_value = safe_param_extract(ID::RD_ARST_VALUE, i * res.width, (ni - i) * res.width); + mrd.srst_value = safe_param_extract(ID::RD_SRST_VALUE, i * res.width, (ni - i) * res.width); + mrd.init_value = safe_param_extract(ID::RD_INIT_VALUE, i * res.width, (ni - i) * res.width); mrd.arst = cell->getPort(ID::RD_ARST).extract(i, 1); mrd.srst = cell->getPort(ID::RD_SRST).extract(i, 1); } if (!is_compat) { - Const transparency_mask = cell->parameters.at(ID::RD_TRANSPARENCY_MASK).extract(i * n_wr_ports, n_wr_ports); - Const collision_x_mask = cell->parameters.at(ID::RD_COLLISION_X_MASK).extract(i * n_wr_ports, n_wr_ports); + Const transparency_mask = safe_param_extract(ID::RD_TRANSPARENCY_MASK, i * n_wr_ports, n_wr_ports); + Const collision_x_mask = safe_param_extract(ID::RD_COLLISION_X_MASK, i * n_wr_ports, n_wr_ports); for (int j = 0; j < n_wr_ports; j++) if (wr_wide_continuation[j] != State::S1) { mrd.transparency_mask.push_back(transparency_mask[j] == State::S1); @@ -799,14 +833,14 @@ namespace { MemWr mwr; mwr.wide_log2 = ceil_log2(ni - i); log_assert(ni - i == (1 << mwr.wide_log2)); - mwr.clk_enable = cell->parameters.at(ID::WR_CLK_ENABLE).extract(i, 1).as_bool(); - mwr.clk_polarity = cell->parameters.at(ID::WR_CLK_POLARITY).extract(i, 1).as_bool(); + mwr.clk_enable = safe_param_extract(ID::WR_CLK_ENABLE, i, 1).as_bool(); + mwr.clk_polarity = safe_param_extract(ID::WR_CLK_POLARITY, i, 1).as_bool(); mwr.clk = cell->getPort(ID::WR_CLK).extract(i, 1); mwr.en = cell->getPort(ID::WR_EN).extract(i * res.width, (ni - i) * res.width); mwr.addr = cell->getPort(ID::WR_ADDR).extract(i * abits, abits); mwr.data = cell->getPort(ID::WR_DATA).extract(i * res.width, (ni - i) * res.width); if (!is_compat) { - Const priority_mask = cell->parameters.at(ID::WR_PRIORITY_MASK).extract(i * n_wr_ports, n_wr_ports); + Const priority_mask = safe_param_extract(ID::WR_PRIORITY_MASK, i * n_wr_ports, n_wr_ports); for (int j = 0; j < n_wr_ports; j++) if (wr_wide_continuation[j] != State::S1) mwr.priority_mask.push_back(priority_mask[j] == State::S1); @@ -832,7 +866,7 @@ namespace { auto &port = res.rd_ports[i]; port.transparency_mask.resize(GetSize(res.wr_ports)); port.collision_x_mask.resize(GetSize(res.wr_ports)); - if (!cell->parameters.at(ID::RD_TRANSPARENT).extract(i, 1).as_bool()) + if (!cell->parameters.at(ID::RD_TRANSPARENT).extract(i, 1, State::S0).as_bool()) continue; if (!port.clk_enable) continue; diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 266aedfe0..622c3d93c 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -4564,6 +4564,46 @@ const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const throw std::out_of_range("Cell::getParam()"); } +// NOTE: as_int() silently truncates >32-bit values and reinterprets string-typed Const values +std::map RTLIL::Cell::getParamsAsInts() const +{ + std::map result; + for (const auto ¶m : parameters) + result[RTLIL::unescape_id(param.first)] = param.second.as_int(); + return result; +} + +double RTLIL::Cell::maxInputConstRatio() const +{ + double max_ratio = 0.0; + for (const auto &conn : connections_) { + if (input(conn.first)) { + double ratio = conn.second.const_ratio(); + if (ratio > max_ratio) + max_ratio = ratio; + } + } + return max_ratio; +} + +std::vector RTLIL::Cell::getOutputPortNames() const +{ + std::vector result; + for (const auto &conn : connections_) { + if (output(conn.first)) + result.push_back(RTLIL::unescape_id(conn.first)); + } + return result; +} + +std::map RTLIL::Cell::getConnectionSizes() const +{ + std::map result; + for (const auto &conn : connections_) + result[RTLIL::unescape_id(conn.first)] = conn.second.size(); + return result; +} + void RTLIL::Cell::sort() { connections_.sort(sort_by_id_str()); @@ -5605,13 +5645,18 @@ bool RTLIL::SigSpec::is_chunk() const return ++it == cs.end(); } -bool RTLIL::SigSpec::is_mostly_const() const +double RTLIL::SigSpec::const_ratio() const { int constbits = 0; for (auto &chunk : chunks()) if (chunk.width > 0 && chunk.wire == NULL) constbits += chunk.width; - return (constbits > size()/2); + return empty() ? 0.0 : static_cast(constbits) / size(); +} + +bool RTLIL::SigSpec::is_mostly_const(double const_ratio_threshold) const +{ + return (const_ratio() > const_ratio_threshold); } bool RTLIL::SigSpec::known_driver() const diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 9dfe0c570..7964ac5a5 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1684,7 +1684,10 @@ public: bool known_driver() const; - bool is_mostly_const() const; + // Constant bit ratio helpers: const_ratio() returns [0.0, 1.0], + // is_mostly_const() returns true if const_ratio() > threshold + double const_ratio() const; + bool is_mostly_const(double const_ratio_threshold = 0.5) const; bool is_fully_const() const; bool is_fully_zero() const; bool is_fully_ones() const; @@ -2529,6 +2532,19 @@ public: void setParam(RTLIL::IdString paramname, RTLIL::Const value); const RTLIL::Const &getParam(RTLIL::IdString paramname) const; + // Primitive-type parameter accessors for efficient Python interop. + // NOTE: silently truncates wide (>32-bit) parameters and reinterprets string-typed Const values + std::map getParamsAsInts() const; + + // Returns the maximum const_ratio() across all input ports, 0.0 if no input ports + double maxInputConstRatio() const; + + // Returns the names of all output ports (backslash-stripped) + std::vector getOutputPortNames() const; + + // Returns {port_name: sig.size()} for all connections, port names backslash-stripped + std::map getConnectionSizes() const; + void sort(); void check(); void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false); diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 113a15bdd..d470d760f 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -444,6 +444,13 @@ struct SimInstance bool did_something = false; sig = sigmap(sig); + if (shared->debug) { + log("GetSize(sig) %s: %d, GetSize(value) %s: %d\n", + log_signal(sig), + GetSize(sig), + log_signal(value), + GetSize(value)); + } log_assert(GetSize(sig) <= GetSize(value)); for (int i = 0; i < GetSize(sig); i++) diff --git a/passes/silimate/negopt.cc b/passes/silimate/negopt.cc index 28d047ed9..c658807b4 100644 --- a/passes/silimate/negopt.cc +++ b/passes/silimate/negopt.cc @@ -60,8 +60,6 @@ struct NegoptPass : public Pass { bool run_pre = false; bool run_post = false; - log_header(design, "Executing NEGOPT pass (optimize negation patterns).\n"); - size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { if (args[argidx] == "-pre") { @@ -76,28 +74,48 @@ struct NegoptPass : public Pass { } extra_args(args, argidx, design); - if (!run_pre && !run_post) { - run_pre = true; - run_post = true; - } + if (run_pre == run_post) + log_cmd_error("NEGOPT requires exactly one of -pre or -post.\n"); + + log_header(design, "Executing NEGOPT %s pass (optimize negation patterns).\n", + run_pre ? "PRE" : "POST"); constexpr int max_iterations = 100; for (auto module : design->selected_modules()) { + auto log_module_event = [&](const char *event) { + log("%s %s\n", event, log_id(module)); + log_flush(); + }; + + auto log_pass_event = [&](const char *event, const char *pass_name, int iter = -1) { + if (iter >= 0) + log(" %s %s pass (iter=%d)\n", event, pass_name, iter + 1); + else + log(" %s %s pass\n", event, pass_name); + log_flush(); + }; + if (run_pre) { + log_module_event("Processing Module:"); + // manual2sub and sub2neg only need to run once: no downstream // pre-subpass creates the patterns they match // separate pm instances so sub2neg sees the $sub cells manual2sub creates. { peepopt_pm pm(module); pm.setup(module->selected_cells()); + log_pass_event("Starting", "manual2sub"); pm.run_manual2sub(); + log_pass_event("Ending", "manual2sub"); log_flush(); } { peepopt_pm pm(module); pm.setup(module->selected_cells()); + log_pass_event("Starting", "sub2neg"); pm.run_sub2neg(); + log_pass_event("Ending", "sub2neg"); log_flush(); } @@ -108,33 +126,51 @@ struct NegoptPass : public Pass { peepopt_pm pm(module); pm.setup(module->selected_cells()); + log_pass_event("Starting", "negexpand", iter); pm.run_negexpand(); + log_pass_event("Ending", "negexpand", iter); log_flush(); + log_pass_event("Starting", "negneg", iter); pm.run_negneg(); + log_pass_event("Ending", "negneg", iter); log_flush(); + log_pass_event("Starting", "negmux", iter); pm.run_negmux(); + log_pass_event("Ending", "negmux", iter); log_flush(); } if (did_something) log_warning("NEGOPT pre reached max iterations (%d) in module %s without convergence.\n", max_iterations, log_id(module)); + + log_module_event("Finished Module:"); } if (run_post) { + log_module_event("Processing Module:"); + did_something = true; for (int iter = 0; iter < max_iterations && did_something; iter++) { did_something = false; peepopt_pm pm(module); pm.setup(module->selected_cells()); + log_pass_event("Starting", "negrebuild", iter); pm.run_negrebuild(); + log_pass_event("Ending", "negrebuild", iter); log_flush(); + log_pass_event("Starting", "muxneg", iter); pm.run_muxneg(); + log_pass_event("Ending", "muxneg", iter); log_flush(); + log_pass_event("Starting", "neg2sub", iter); pm.run_neg2sub(); + log_pass_event("Ending", "neg2sub", iter); log_flush(); } if (did_something) log_warning("NEGOPT post reached max iterations (%d) in module %s without convergence.\n", max_iterations, log_id(module)); + + log_module_event("Finished Module:"); } } } diff --git a/passes/silimate/peepopt_manual2sub.pmg b/passes/silimate/peepopt_manual2sub.pmg index b45a05308..257c93b86 100644 --- a/passes/silimate/peepopt_manual2sub.pmg +++ b/passes/silimate/peepopt_manual2sub.pmg @@ -94,7 +94,7 @@ code root_add inner_add_A not_gate_A subtrahend minuend result_sig is_signed subtrahend = port(not_gate_A, \A); - log("manual2sub in %s: Found (a + ~b) + 1 pattern, creating $sub for %s\n", log_id(module), log_signal(result_sig)); + log(" creating $sub for %s from (a + ~b) + 1\n", log_signal(result_sig)); Cell *cell = root_add; int width = GetSize(result_sig); int inner_width = GetSize(inner_y); @@ -196,7 +196,7 @@ code root_add inner_add_B not_gate_B minuend subtrahend result_sig is_signed else minuend = root_a; - log("manual2sub in %s: Found a + (~b + 1) pattern, creating $sub for %s\n", log_id(module), log_signal(result_sig)); + log(" creating $sub for %s from a + (~b + 1)\n", log_signal(result_sig)); Cell *cell = root_add; int width = GetSize(result_sig); int inner_width = GetSize(inner_add_B->getPort(ID::Y)); diff --git a/passes/silimate/peepopt_muxneg.pmg b/passes/silimate/peepopt_muxneg.pmg index e81fc7971..5d03ad7e9 100644 --- a/passes/silimate/peepopt_muxneg.pmg +++ b/passes/silimate/peepopt_muxneg.pmg @@ -60,8 +60,8 @@ code mux_a mux_b mux_s mux_y neg_a_in neg_a_y neg_b_in neg_b_y neg_a_signed neg_ neg_out_rs.extend_u0(GetSize(mux_y), neg_a_signed); module->connect(mux_y, neg_out_rs); - log("muxneg pattern in %s: mux=%s, neg_a=%s, neg_b=%s\n", - log_id(module), log_id(mux), log_id(neg_a), log_id(neg_b)); + log(" mux=%s, neg_a=%s, neg_b=%s\n", + log_id(mux), log_id(neg_a), log_id(neg_b)); new_mux->fixup_parameters(); new_neg->fixup_parameters(); diff --git a/passes/silimate/peepopt_neg2sub.pmg b/passes/silimate/peepopt_neg2sub.pmg index 9594e3b47..13656d9aa 100644 --- a/passes/silimate/peepopt_neg2sub.pmg +++ b/passes/silimate/peepopt_neg2sub.pmg @@ -62,8 +62,8 @@ code add_a add_b add_y neg_a neg_y neg_on_a add_a_signed add_b_signed neg_signed add->setPort(\Y, add_y); add->type = $sub; - log("neg2sub pattern in %s: add=%s, neg=%s (safe sub replacement)\n", - log_id(module), log_id(add), log_id(neg)); + log(" add=%s, neg=%s (safe sub replacement)\n", + log_id(add), log_id(neg)); add->fixup_parameters(); autoremove(neg); diff --git a/passes/silimate/peepopt_negexpand.pmg b/passes/silimate/peepopt_negexpand.pmg index 7ddc0b950..df7c90adc 100644 --- a/passes/silimate/peepopt_negexpand.pmg +++ b/passes/silimate/peepopt_negexpand.pmg @@ -49,8 +49,7 @@ code neg_a neg_y add_a add_b a_signed Cell *new_add = module->addAdd(NEW_ID2_SUFFIX("add"), neg_add_a, neg_add_b, neg_y, a_signed); - log("negexpand pattern in %s: neg=%s, add=%s\n", - log_id(module), log_id(neg), log_id(add)); + log(" neg=%s, add=%s\n", log_id(neg), log_id(add)); neg_a_cell->fixup_parameters(); neg_b_cell->fixup_parameters(); diff --git a/passes/silimate/peepopt_negmux.pmg b/passes/silimate/peepopt_negmux.pmg index d1918e3bf..fbedbf507 100644 --- a/passes/silimate/peepopt_negmux.pmg +++ b/passes/silimate/peepopt_negmux.pmg @@ -60,8 +60,7 @@ code neg_a neg_y mux_a mux_b mux_s mux_y a_signed Cell *new_mux = module->addMux(NEW_ID2_SUFFIX("mux"), neg_mux_a, neg_mux_b, mux_s, neg_y); - log("negmux pattern in %s: neg=%s, mux=%s\n", - log_id(module), log_id(neg), log_id(mux)); + log(" neg=%s, mux=%s\n", log_id(neg), log_id(mux)); neg_a_cell->fixup_parameters(); neg_b_cell->fixup_parameters(); diff --git a/passes/silimate/peepopt_negneg.pmg b/passes/silimate/peepopt_negneg.pmg index 166e641b0..09d7aa543 100644 --- a/passes/silimate/peepopt_negneg.pmg +++ b/passes/silimate/peepopt_negneg.pmg @@ -29,8 +29,7 @@ code neg1_a neg1_y neg2_a module->connect(neg1_y, neg2_a); - log("negneg pattern in %s: neg1=%s, neg2=%s\n", - log_id(module), log_id(neg1), log_id(neg2)); + log(" neg1=%s, neg2=%s\n", log_id(neg1), log_id(neg2)); autoremove(neg1); autoremove(neg2); diff --git a/passes/silimate/peepopt_negrebuild.pmg b/passes/silimate/peepopt_negrebuild.pmg index 37c8fba5e..49683f09f 100644 --- a/passes/silimate/peepopt_negrebuild.pmg +++ b/passes/silimate/peepopt_negrebuild.pmg @@ -100,8 +100,8 @@ code add_a add_b add_y neg1_a neg1_y neg2_a neg2_y add_signed add_b_signed neg1_ neg_out_rs.extend_u0(GetSize(add_y), add_signed); module->connect(add_y, neg_out_rs); - log("negrebuild pattern in %s: add=%s, neg1=%s, neg2=%s\n", - log_id(module), log_id(add), log_id(neg1), log_id(neg2)); + log(" add=%s, neg1=%s, neg2=%s\n", + log_id(add), log_id(neg1), log_id(neg2)); new_add->fixup_parameters(); new_neg->fixup_parameters(); diff --git a/passes/silimate/peepopt_sub2neg.pmg b/passes/silimate/peepopt_sub2neg.pmg index c0921c290..8b8aff9dd 100644 --- a/passes/silimate/peepopt_sub2neg.pmg +++ b/passes/silimate/peepopt_sub2neg.pmg @@ -43,8 +43,8 @@ code sub_a sub_b sub_y a_signed b_signed sub->setPort(\Y, sub_y); sub->type = $add; - log("sub2neg pattern in %s: sub=%s -> neg=%s, add=%s\n", - log_id(module), log_id(sub), log_id(neg), log_id(sub)); + log(" sub=%s -> neg=%s, add=%s\n", + log_id(sub), log_id(neg), log_id(sub)); sub->fixup_parameters(); neg->fixup_parameters();