From f218b5ba580d9f3bf3919635f4b4146a3887e484 Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Fri, 4 Apr 2025 03:20:07 -0700 Subject: [PATCH] Revert "Represent memory size with size_t" This reverts commit bb5f8415afa160e989242b65acae668334e322b7. --- backends/json/json.cc | 2 +- backends/rtlil/rtlil_backend.cc | 2 +- backends/verilog/verilog_backend.cc | 4 ++-- frontends/verific/verific.cc | 11 +++++++---- kernel/mem.cc | 8 ++++---- kernel/mem.h | 5 ++--- kernel/rtlil.cc | 24 ------------------------ kernel/rtlil.h | 5 +---- passes/memory/memory_bram.cc | 2 +- passes/memory/memory_libmap.cc | 4 ++-- passes/memory/memory_map.cc | 6 +++--- passes/proc/proc_rom.cc | 2 +- passes/sat/sim.cc | 20 ++++++++++---------- 13 files changed, 35 insertions(+), 60 deletions(-) diff --git a/backends/json/json.cc b/backends/json/json.cc index b66e95a03..749fe1fc3 100644 --- a/backends/json/json.cc +++ b/backends/json/json.cc @@ -252,7 +252,7 @@ struct JsonWriter f << stringf("\n },\n"); f << stringf(" \"width\": %d,\n", it.second->width); f << stringf(" \"start_offset\": %d,\n", it.second->start_offset); - f << stringf(" \"size\": %zu\n", it.second->size); + f << stringf(" \"size\": %d\n", it.second->size); f << stringf(" }"); first = false; } diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc index 0fae0da8f..113f1a615 100644 --- a/backends/rtlil/rtlil_backend.cc +++ b/backends/rtlil/rtlil_backend.cc @@ -158,7 +158,7 @@ void RTLIL_BACKEND::dump_memory(std::ostream &f, std::string indent, const RTLIL if (memory->width != 1) f << stringf("width %d ", memory->width); if (memory->size != 0) - f << stringf("size %zu ", memory->size); + f << stringf("size %d ", memory->size); if (memory->start_offset != 0) f << stringf("offset %d ", memory->start_offset); f << stringf("%s\n", memory->name.c_str()); diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index bab5d2e9a..0dfd4d96b 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -460,7 +460,7 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem) std::string mem_id = id(mem.memid); dump_attributes(f, indent, mem.attributes); - f << stringf("%s" "reg [%d:0] %s [%zu:%d];\n", indent.c_str(), mem.width-1, mem_id.c_str(), mem.size+mem.start_offset-1, mem.start_offset); + f << stringf("%s" "reg [%d:0] %s [%d:%d];\n", indent.c_str(), mem.width-1, mem_id.c_str(), mem.size+mem.start_offset-1, mem.start_offset); // for memory block make something like: // reg [7:0] memid [3:0]; @@ -497,7 +497,7 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem) else { Const data = mem.get_init_data(); - for (size_t i=0; imemories[memory->name] = memory; import_attributes(memory->attributes, net, nl); - size_t number_of_bits = net->Size(); - size_t bits_in_word = number_of_bits; + uint64_t number_of_bits = net->Size(); + uint64_t bits_in_word = number_of_bits; FOREACH_PORTREF_OF_NET(net, si, pr) { if (pr->GetInst()->Type() == OPER_READ_PORT) { - bits_in_word = min(bits_in_word, pr->GetInst()->OutputSize()); + bits_in_word = min(bits_in_word, pr->GetInst()->OutputSize()); continue; } if (pr->GetInst()->Type() == OPER_WRITE_PORT || pr->GetInst()->Type() == OPER_CLOCKED_WRITE_PORT) { - bits_in_word = min(bits_in_word, pr->GetInst()->Input2Size()); + bits_in_word = min(bits_in_word, pr->GetInst()->Input2Size()); continue; } log_error("Verific RamNet %s is connected to unsupported instance type %s (%s).\n", net->Name(), pr->GetInst()->View()->Owner()->Name(), pr->GetInst()->Name()); } + if ((bits_in_word * number_of_bits) > (uint64_t)(((uint64_t)1) << 28)) + log_error("Memory %s size is larger than 2**28 bits, bits_in_word: %ld, number_of_bits: %ld, total: %ld\n", net->Name(), + bits_in_word, number_of_bits, bits_in_word * number_of_bits); memory->width = bits_in_word; memory->size = number_of_bits / bits_in_word; diff --git a/kernel/mem.cc b/kernel/mem.cc index 545860277..67501acfd 100644 --- a/kernel/mem.cc +++ b/kernel/mem.cc @@ -130,7 +130,7 @@ void Mem::emit() { cell->parameters[ID::MEMID] = Const(memid.str()); cell->parameters[ID::WIDTH] = Const(width); cell->parameters[ID::OFFSET] = Const(start_offset); - cell->parameters[ID::SIZE] = Const(size, 64); + cell->parameters[ID::SIZE] = Const(size); Const rd_wide_continuation, rd_clk_enable, rd_clk_polarity, rd_transparency_mask, rd_collision_x_mask; Const wr_wide_continuation, wr_clk_enable, wr_clk_polarity, wr_priority_mask; Const rd_ce_over_srst, rd_arst_value, rd_srst_value, rd_init_value; @@ -696,7 +696,7 @@ namespace { Mem res(cell->module, cell->parameters.at(ID::MEMID).decode_string(), cell->parameters.at(ID::WIDTH).as_int(), cell->parameters.at(ID::OFFSET).as_int(), - cell->parameters.at(ID::SIZE).as_size() + cell->parameters.at(ID::SIZE).as_int() ); bool is_compat = cell->type == ID($mem); int abits = cell->parameters.at(ID::ABITS).as_int(); @@ -705,13 +705,13 @@ namespace { res.attributes = cell->attributes; Const &init = cell->parameters.at(ID::INIT); if (!init.is_fully_undef()) { - size_t pos = 0; + int pos = 0; while (pos < res.size) { Const word = init.extract(pos * res.width, res.width, State::Sx); if (word.is_fully_undef()) { pos++; } else { - size_t epos; + int epos; for (epos = pos; epos < res.size; epos++) { Const eword = init.extract(epos * res.width, res.width, State::Sx); if (eword.is_fully_undef()) diff --git a/kernel/mem.h b/kernel/mem.h index e841f17d5..a06f44bd8 100644 --- a/kernel/mem.h +++ b/kernel/mem.h @@ -95,8 +95,7 @@ struct Mem : RTLIL::AttrObject { bool packed; RTLIL::Memory *mem; Cell *cell; - size_t size; - int width, start_offset; + int width, start_offset, size; std::vector inits; std::vector rd_ports; std::vector wr_ports; @@ -223,7 +222,7 @@ struct Mem : RTLIL::AttrObject { // in the same clock domain. void emulate_read_first(FfInitVals *initvals); - Mem(Module *module, IdString memid, int width, int start_offset, size_t size) : module(module), memid(memid), packed(false), mem(nullptr), cell(nullptr), size(size), width(width), start_offset(start_offset) {} + Mem(Module *module, IdString memid, int width, int start_offset, int size) : module(module), memid(memid), packed(false), mem(nullptr), cell(nullptr), width(width), start_offset(start_offset), size(size) {} }; // MemContents efficiently represents the contents of a potentially sparse memory by storing only those segments that are actually defined diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 7ccbc87c0..6659417d5 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -236,19 +236,6 @@ RTLIL::Const::Const(int val, int width) } } -RTLIL::Const::Const(size_t val) -{ - flags = RTLIL::CONST_FLAG_NONE; - new ((void*)&bits_) bitvectype(); - tag = backing_tag::bits; - bitvectype& bv = get_bits(); - bv.reserve(64); - for (int i = 0; i < 64; i++) { - bv.push_back((val & 1) != 0 ? State::S1 : State::S0); - val = val >> 1; - } -} - RTLIL::Const::Const(RTLIL::State bit, int width) { flags = RTLIL::CONST_FLAG_NONE; @@ -395,17 +382,6 @@ int RTLIL::Const::as_int(bool is_signed) const return ret; } -size_t RTLIL::Const::as_size() const -{ - bitvectorize(); - bitvectype& bv = get_bits(); - size_t ret = 0; - for (size_t i = 0; i < bv.size() && i < 32; i++) - if (bv[i] == State::S1) - ret |= 1 << i; - return ret; -} - int RTLIL::Const::get_min_size(bool is_signed) const { if (empty()) return 0; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index f4b874a1f..7c5640c6c 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -720,7 +720,6 @@ public: Const() : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(std::vector()) {} Const(const std::string &str); Const(int val, int width = 32); - Const(size_t val); Const(RTLIL::State bit, int width = 1); Const(const std::vector &bits) : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(bits) {} Const(const std::vector &bits); @@ -736,7 +735,6 @@ public: std::vector& bits(); bool as_bool() const; int as_int(bool is_signed = false) const; - size_t as_size() const; std::string as_string(const char* any = "-") const; static Const from_string(const std::string &str); std::vector to_bits() const; @@ -1718,8 +1716,7 @@ struct RTLIL::Memory : public RTLIL::AttrObject Memory(); RTLIL::IdString name; - size_t size; - int width, start_offset; + int width, start_offset, size; #ifdef WITH_PYTHON ~Memory(); static std::map *get_all_memorys(void); diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index 41e30f13e..9db329c5c 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -807,7 +807,7 @@ grow_read_ports:; if (cell_init) { Const initparam = mem.get_init_data(); initdata.reserve(mem.size); - for (size_t i = 0; i < mem.size; i++) { + for (int i = 0; i < mem.size; i++) { std::vector val; for (auto idx : shuffle_map) { if (idx == -1) diff --git a/passes/memory/memory_libmap.cc b/passes/memory/memory_libmap.cc index 23111674b..b0d0498ea 100644 --- a/passes/memory/memory_libmap.cc +++ b/passes/memory/memory_libmap.cc @@ -2098,11 +2098,11 @@ void MemMapping::emit(const MemConfig &cfg) { if (!bit.valid) { initval.push_back(State::Sx); } else { - size_t addr = bit.addr; + int addr = bit.addr; for (int i = GetSize(cfg.def->dbits) - 1; i < cfg.def->abits; i++) if (hwa & 1 << i) addr += 1 << hw_addr_swizzle[i]; - if (addr >= (size_t) mem.start_offset && addr < mem.start_offset + mem.size) + if (addr >= mem.start_offset && addr < mem.start_offset + mem.size) initval.push_back(init_data[(addr - mem.start_offset) * mem.width + bit.bit]); else initval.push_back(State::Sx); diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 37654c25a..ba741d4ea 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -201,7 +201,7 @@ struct MemoryMapWorker int count_static = 0; - for (size_t i = 0; i < mem.size; i++) + for (int i = 0; i < mem.size; i++) { int addr = i + mem.start_offset; int idx = addr & ((1 << abits) - 1); @@ -268,7 +268,7 @@ struct MemoryMapWorker } } - log(" created %zu %s cells and %d static cells of width %d.\n", + log(" created %d %s cells and %d static cells of width %d.\n", mem.size-count_static, formal && (static_only || async_wr) ? "$ff" : "$dff", count_static, mem.width); int count_dff = 0, count_mux = 0, count_wrmux = 0; @@ -315,7 +315,7 @@ struct MemoryMapWorker if (!static_only) { - for (size_t i = 0; i < mem.size; i++) + for (int i = 0; i < mem.size; i++) { int addr = i + mem.start_offset; int idx = addr & ((1 << abits) - 1); diff --git a/passes/proc/proc_rom.cc b/passes/proc/proc_rom.cc index 8d019fe73..5f8e47ceb 100644 --- a/passes/proc/proc_rom.cc +++ b/passes/proc/proc_rom.cc @@ -156,7 +156,7 @@ struct RomWorker mem.attributes = sw->attributes; Const init_data; - for (size_t i = 0; i < mem.size; i++) { + for (int i = 0; i < mem.size; i++) { auto it = vals.find(i); if (it == vals.end()) { log_assert(got_default); diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 441a0e08a..10eb7b033 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -486,8 +486,8 @@ struct SimInstance bool dirty = false; - size_t offset = (addr - state.mem->start_offset) * state.mem->width; - for (size_t i = 0; i < data.as_size(); i++) + int offset = (addr - state.mem->start_offset) * state.mem->width; + for (int i = 0; i < GetSize(data); i++) if (0 <= i+offset && i+offset < state.mem->size * state.mem->width && data[i] != State::Sa) if (state.data[i+offset] != data[i]) dirty = true, state.data.bits()[i+offset] = data[i]; @@ -496,11 +496,11 @@ struct SimInstance dirty_memories.insert(memid); } - void set_memory_state_bit(IdString memid, size_t offset, State data) + void set_memory_state_bit(IdString memid, int offset, State data) { auto &state = mem_database[memid]; if (offset >= state.mem->size * state.mem->width) - log_error("Addressing out of bounds bit %zux/%zu of memory %s\n", offset, state.mem->size * state.mem->width, log_id(memid)); + log_error("Addressing out of bounds bit %d/%d of memory %s\n", offset, state.mem->size * state.mem->width, log_id(memid)); if (state.data[offset] != data) { state.data.bits()[offset] = data; dirty_memories.insert(memid); @@ -604,11 +604,11 @@ struct SimInstance if (addr.is_fully_def()) { int addr_int = addr.as_int(); - size_t index = addr_int - mem.start_offset; + int index = addr_int - mem.start_offset; if (index >= 0 && index < mem.size) data = mdb.data.extract(index*mem.width, mem.width << port.wide_log2); - for (size_t offset = 0; offset < 1 << port.wide_log2; offset++) { + for (int offset = 0; offset < 1 << port.wide_log2; offset++) { register_memory_addr(id, addr_int + offset); } } @@ -768,7 +768,7 @@ struct SimInstance if (addr.is_fully_def()) { int addr_int = addr.as_int(); - size_t index = addr_int - mem.start_offset; + int index = addr_int - mem.start_offset; if (index >= 0 && index < mem.size) for (int i = 0; i < (mem.width << port.wide_log2); i++) if (enable[i] == State::S1 && mdb.data.at(index*mem.width+i) != data[i]) { @@ -1093,7 +1093,7 @@ struct SimInstance { auto &mdb = mem_database.at(memid); auto &mem = *mdb.mem; - size_t index = addr - mem.start_offset; + int index = addr - mem.start_offset; if (index < 0 || index >= mem.size) return; auto it = trace_mem_database.find(memid); @@ -1901,7 +1901,7 @@ struct SimWorker : SimShared word_path.back() = addr_part; int addr; word_path.get_address(addr); - if (addr < item.mem->start_offset || ((size_t) addr - item.mem->start_offset) >= item.mem->size) + if (addr < item.mem->start_offset || (addr - item.mem->start_offset) >= item.mem->size) continue; bool inserted = hierarchy.paths.emplace(word_path, {instance, nullptr, item.mem->memid, addr}).second; if (!inserted) @@ -2258,7 +2258,7 @@ struct SimWorker : SimShared data_file << stringf("%s",fst->valueOf(item.second).c_str()); for(auto &item : outputs) data_file << stringf("%s",fst->valueOf(item.second).c_str()); - data_file << stringf("%s\n",Const(time-prev_time, 32).as_string().c_str()); + data_file << stringf("%s\n",Const(time-prev_time).as_string().c_str()); if (time==startCount) { // initial state