diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc
index 262105bd0..1ecd51cd8 100644
--- a/frontends/liberty/liberty.cc
+++ b/frontends/liberty/liberty.cc
@@ -210,7 +210,6 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node)
 {
 	auto [iq_sig, iqn_sig] = find_latch_ff_wires(module, node);
 	RTLIL::SigSpec clk_sig, data_sig, clear_sig, preset_sig;
-	bool clk_polarity = true, clear_polarity = true, preset_polarity = true;
 	const std::string name = module->name.unescape();
 
 	std::optional<char> clear_preset_var1;
@@ -250,21 +249,21 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node)
 		cell->setPort(ID::C, clk_sig);
 
 		if (clear_sig.size() == 0 && preset_sig.size() == 0) {
-			cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N');
+			cell->type = stringf("$_DFF_P_");
 		}
 
 		if (clear_sig.size() == 1 && preset_sig.size() == 0) {
-			cell->type = stringf("$_DFF_%c%c0_", clk_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N');
+			cell->type = stringf("$_DFF_PP0_");
 			cell->setPort(ID::R, clear_sig);
 		}
 
 		if (clear_sig.size() == 0 && preset_sig.size() == 1) {
-			cell->type = stringf("$_DFF_%c%c1_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N');
+			cell->type = stringf("$_DFF_PP1_");
 			cell->setPort(ID::R, preset_sig);
 		}
 
 		if (clear_sig.size() == 1 && preset_sig.size() == 1) {
-			cell->type = stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N');
+			cell->type = stringf("$_DFFSR_PPP_");
 
 			SigBit s_sig = preset_sig;
 			SigBit r_sig = clear_sig;
@@ -301,7 +300,6 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
 {
 	auto [iq_sig, iqn_sig] = find_latch_ff_wires(module, node);
 	RTLIL::SigSpec enable_sig, data_sig, clear_sig, preset_sig;
-	bool enable_polarity = true, clear_polarity = true, preset_polarity = true;
 
 	for (auto child : node->children) {
 		if (child->id == "enable")
@@ -327,63 +325,18 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
 	cell->setPort(ID::A, iq_sig);
 	cell->setPort(ID::Y, iqn_sig);
 
-	if (clear_sig.size() == 1)
-	{
-		RTLIL::SigSpec clear_negative = clear_sig;
-		RTLIL::SigSpec clear_enable = clear_sig;
-
-		if (clear_polarity == true || clear_polarity != enable_polarity)
-		{
-			RTLIL::Cell *inv = module->addCell(NEW_ID, ID($_NOT_));
-			inv->setPort(ID::A, clear_sig);
-			inv->setPort(ID::Y, module->addWire(NEW_ID));
-
-			if (clear_polarity == true)
-				clear_negative = inv->getPort(ID::Y);
-			if (clear_polarity != enable_polarity)
-				clear_enable = inv->getPort(ID::Y);
-		}
-
-		RTLIL::Cell *data_gate = module->addCell(NEW_ID, ID($_AND_));
-		data_gate->setPort(ID::A, data_sig);
-		data_gate->setPort(ID::B, clear_negative);
-		data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
-
-		RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? ID($_OR_) : ID($_AND_));
-		enable_gate->setPort(ID::A, enable_sig);
-		enable_gate->setPort(ID::B, clear_enable);
-		enable_gate->setPort(ID::Y, enable_sig = module->addWire(NEW_ID));
+	if (clear_sig.size() == 1) {
+		RTLIL::SigSpec clear_negative = module->NotGate(NEW_ID, clear_sig);
+		data_sig = module->AndGate(NEW_ID, data_sig, clear_negative);
+		enable_sig = module->OrGate(NEW_ID, enable_sig, clear_sig);
 	}
 
-	if (preset_sig.size() == 1)
-	{
-		RTLIL::SigSpec preset_positive = preset_sig;
-		RTLIL::SigSpec preset_enable = preset_sig;
-
-		if (preset_polarity == false || preset_polarity != enable_polarity)
-		{
-			RTLIL::Cell *inv = module->addCell(NEW_ID, ID($_NOT_));
-			inv->setPort(ID::A, preset_sig);
-			inv->setPort(ID::Y, module->addWire(NEW_ID));
-
-			if (preset_polarity == false)
-				preset_positive = inv->getPort(ID::Y);
-			if (preset_polarity != enable_polarity)
-				preset_enable = inv->getPort(ID::Y);
-		}
-
-		RTLIL::Cell *data_gate = module->addCell(NEW_ID, ID($_OR_));
-		data_gate->setPort(ID::A, data_sig);
-		data_gate->setPort(ID::B, preset_positive);
-		data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
-
-		RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? ID($_OR_) : ID($_AND_));
-		enable_gate->setPort(ID::A, enable_sig);
-		enable_gate->setPort(ID::B, preset_enable);
-		enable_gate->setPort(ID::Y, enable_sig = module->addWire(NEW_ID));
+	if (preset_sig.size() == 1) {
+		data_sig = module->OrGate(NEW_ID, data_sig, preset_sig);
+		enable_sig = module->OrGate(NEW_ID, enable_sig, preset_sig);
 	}
 
-	cell = module->addCell(NEW_ID, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N'));
+	cell = module->addCell(NEW_ID, stringf("$_DLATCH_P_"));
 	cell->setPort(ID::D, data_sig);
 	cell->setPort(ID::Q, iq_sig);
 	cell->setPort(ID::E, enable_sig);