From eefdcbfe8192eb45fc5cd6006a428906c1fac8b3 Mon Sep 17 00:00:00 2001
From: William Zhu <williamzhu@Williams-MacBook-Pro.local>
Date: Thu, 27 Mar 2025 15:23:18 -0700
Subject: [PATCH] added ornot tests

---
 tests/silimate/mux_andnot.ys |   2 +-
 tests/silimate/mux_ornot.ys  | 224 +++++++++++++++++++++++++++++++++++
 2 files changed, 225 insertions(+), 1 deletion(-)
 create mode 100644 tests/silimate/mux_ornot.ys

diff --git a/tests/silimate/mux_andnot.ys b/tests/silimate/mux_andnot.ys
index a0d67ba49..f3bac89a1 100644
--- a/tests/silimate/mux_andnot.ys
+++ b/tests/silimate/mux_andnot.ys
@@ -128,8 +128,8 @@ equiv_opt -assert opt_expr -mux_bool
 # Check final design has correct number of gates
 design -load postopt
 select -assert-count 1 t:$and
-select -assert-count 1 t:$or
 select -assert-count 1 t:$not
+select -assert-count 1 t:$or
 
 design -reset
 log -pop
diff --git a/tests/silimate/mux_ornot.ys b/tests/silimate/mux_ornot.ys
new file mode 100644
index 000000000..d4bba79e2
--- /dev/null
+++ b/tests/silimate/mux_ornot.ys
@@ -0,0 +1,224 @@
+log -header "Simple positive case"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire a,
+  input wire s,
+  output wire x
+);
+  assign x = s ? a : 1'b1;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after opt_expr
+equiv_opt -assert opt_expr -mux_bool
+
+# Check final design has correct number of gates
+design -load postopt
+select -assert-count 1 t:$or
+select -assert-count 1 t:$not
+
+design -reset
+log -pop
+
+
+
+log -header "Case with inverted a"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire a,
+  input wire s,
+  output wire x
+);
+  assign x = s ? ~a : 1'b1;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after opt_expr
+equiv_opt -assert opt_expr -mux_bool
+
+# Check final design has correct number of gates
+design -load postopt
+select -assert-count 1 t:$or
+select -assert-count 2 t:$not
+
+design -reset
+log -pop
+
+
+
+log -header "Case with inverted s"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire a,
+  input wire s,
+  output wire x
+);
+  assign x = ~s ? 1'b1 : a;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after opt_expr
+equiv_opt -assert opt_expr -mux_bool
+
+# Check final design has correct number of gates
+# Did not include check for not count since we have an unassigned ~s wire
+# TODO check
+design -load postopt
+write_verilog dump.v
+select -assert-count 1 t:$or
+
+design -reset
+log -pop
+
+
+
+log -header "Nested AND gates"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire a,
+  input wire b,
+  input wire s,
+  output wire x
+);
+  assign x = s ? a & b : 1'b1;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after opt_expr
+equiv_opt -assert opt_expr -mux_bool
+
+# Check final design has correct number of gates
+design -load postopt
+select -assert-count 1 t:$and
+select -assert-count 1 t:$not
+select -assert-count 1 t:$or
+
+design -reset
+log -pop
+
+
+
+log -header "Nested OR gates"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire a,
+  input wire b,
+  input wire s,
+  output wire x
+);
+  assign x = s ? a | b : 1'b1;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after opt_expr
+equiv_opt -assert opt_expr -mux_bool
+
+# Check final design has correct number of gates
+design -load postopt
+select -assert-count 1 t:$not
+select -assert-count 2 t:$or
+
+design -reset
+log -pop
+
+
+
+log -header "Nested muxes"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire a,
+  input wire s1,
+  input wire s2,
+  output wire x
+);
+  assign x = s1 ? (s2 ? a : 1'b1) : 1'b1;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after opt_expr
+equiv_opt -assert opt_expr -mux_bool
+
+# Check final design has correct number of gates
+design -load postopt
+select -assert-count 2 t:$not
+select -assert-count 2 t:$or
+
+design -reset
+log -pop
+
+
+
+log -header "With constant propagation"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire a,
+  input wire s,
+  output wire x
+);
+  assign x = s ? a & 1'b1 : 1'b1;
+endmodule
+EOF
+check -assert
+
+# Check equivalence after opt_expr
+equiv_opt -assert opt_expr -mux_bool
+
+# Check final design has correct number of gates
+design -load postopt
+select -assert-count 1 t:$not
+select -assert-count 1 t:$or
+
+design -reset
+log -pop
+
+
+
+log -header "With multibit constant"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire a,
+  input wire s,
+  output wire x
+);
+  assign x = s ? a : 32'b1;
+endmodule
+EOF
+check -assert
+
+# Runs wreduce to reduce width of the constant before applying opt_expr
+# Without this line, this test case will not pass
+# Believe it is intended behavior to not optimize constant with more than one bit
+wreduce
+
+# Check equivalence after opt_expr
+equiv_opt -assert opt_expr -mux_bool
+
+# Check final design has correct number of gates
+design -load postopt
+select -assert-count 1 t:$not
+select -assert-count 1 t:$or
+
+design -reset
+log -pop
\ No newline at end of file