diff --git a/tests/alumacc/cmp_merge.ys b/tests/alumacc/cmp_merge.ys
index ae46ba883..fb79822f5 100644
--- a/tests/alumacc/cmp_merge.ys
+++ b/tests/alumacc/cmp_merge.ys
@@ -40,4 +40,3 @@ EOT
 hierarchy
 wreduce
 equiv_opt -assert alumacc
-
diff --git a/tests/arch/nexus/dsp_equiv.sv b/tests/arch/nexus/dsp_equiv.sv
index 88eb8bb21..4d991eec8 100644
--- a/tests/arch/nexus/dsp_equiv.sv
+++ b/tests/arch/nexus/dsp_equiv.sv
@@ -27,7 +27,7 @@ endmodule
 module mul_pipe_u (input clk, input [8:0] a, b, output reg [17:0] y);
 	reg [8:0] a_r;
 	reg [8:0] b_r;
-	always @(posedge clk) begin 
+	always @(posedge clk) begin
 		a_r <= a;
 		b_r <= b;
 		y <= a_r * b_r;
diff --git a/tests/arch/nexus/pipe_mul.sv b/tests/arch/nexus/pipe_mul.sv
index 75769a29c..4af42425b 100644
--- a/tests/arch/nexus/pipe_mul.sv
+++ b/tests/arch/nexus/pipe_mul.sv
@@ -153,4 +153,4 @@ module mul18_two_clock (
 	always_ff @(posedge clk0) a_r <= a;
 	always_ff @(posedge clk1) b_r <= b;
 	assign y = a_r * b_r;
-endmodule
\ No newline at end of file
+endmodule
diff --git a/tests/arch/nexus/pipe_mul.ys b/tests/arch/nexus/pipe_mul.ys
index c5e40b96e..702847be2 100644
--- a/tests/arch/nexus/pipe_mul.ys
+++ b/tests/arch/nexus/pipe_mul.ys
@@ -71,4 +71,4 @@ design -load pristine
 hierarchy -top mul18_two_clock
 synth_nexus -family lifcl -top mul18_two_clock
 select -assert-count 1 t:MULT18X18 r:REGINPUTA=BYPASS r:REGINPUTB=BYPASS
-select -assert-min 1 t:FD1P3*
\ No newline at end of file
+select -assert-min 1 t:FD1P3*
diff --git a/tests/opt/opt_muxtree_port_reconverge.ys b/tests/opt/opt_muxtree_port_reconverge.ys
index 592786dfc..b31d40d3d 100644
--- a/tests/opt/opt_muxtree_port_reconverge.ys
+++ b/tests/opt/opt_muxtree_port_reconverge.ys
@@ -17,7 +17,7 @@ module \top
     connect \S \b
     connect \Y \y
   end
-  
+
   attribute \full_case 1
   cell $pmux \pmux
     parameter \WIDTH 1
@@ -27,7 +27,7 @@ module \top
     connect \S { \n_a \s }
     connect \Y \q
   end
-  
+
   attribute \full_case 1
   cell $not \not
     parameter \A_SIGNED 0
diff --git a/tests/symfpu/edges.sv b/tests/symfpu/edges.sv
index 5be02d3bd..382c94562 100644
--- a/tests/symfpu/edges.sv
+++ b/tests/symfpu/edges.sv
@@ -147,7 +147,7 @@ module edges(input clk);
     wire lhs_norm = a_norm;
     wire lhs_subnorm = a_subnorm;
     wire lhs_finite = a_finite;
-    
+
     wire rhs_sign = b_sign;
     wire [30:0] rhs_unsigned = b_unsigned;
     wire [7:0] rhs_exp = b_exp;
diff --git a/tests/techmap/dfflibmap_resetval_clobber.ys b/tests/techmap/dfflibmap_resetval_clobber.ys
index aacf40f6c..c09eefa22 100644
--- a/tests/techmap/dfflibmap_resetval_clobber.ys
+++ b/tests/techmap/dfflibmap_resetval_clobber.ys
@@ -10,4 +10,4 @@ flatten -noscopeinfo
 opt_clean
 
 select -assert-count 1 t:* top %i
-select -assert-count 1 t:$_DFF_PP0_ top %i
\ No newline at end of file
+select -assert-count 1 t:$_DFF_PP0_ top %i
diff --git a/tests/various/hierarchy_recursive.v b/tests/various/hierarchy_recursive.v
index 9d4fd323c..9e68528fa 100644
--- a/tests/various/hierarchy_recursive.v
+++ b/tests/various/hierarchy_recursive.v
@@ -1,3 +1,3 @@
 module top(input x, output y);
 top top_i(.x(x), .y(y));
-endmodule
\ No newline at end of file
+endmodule