From eb83c40d2451cbd58a98d29f54d6e1b01654f283 Mon Sep 17 00:00:00 2001 From: Chia-Hsiang Chang Date: Tue, 12 May 2026 00:07:00 -0700 Subject: [PATCH] fix: check the cell is a child node before skipping --- passes/sat/sim.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index be689d218..ffa141d65 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -651,8 +651,8 @@ struct SimInstance // If the cell is a blackbox child of an instance root module, skip it if (shared->blackbox_children) { - Module *m = module->design->module(cell->type); - if (m) + Module *mod = module->design->module(cell->type); + if (shared->instance_root_modules.count(mod->name)) return; } @@ -1614,7 +1614,7 @@ struct SimWorker : SimShared fstHandle id = fst->getHandle(iscope + "." + RTLIL::unescape_id(wire->name)); if (id == 0) { log_error("Can't find port '%s' on module '%s' in FST.\n", - (iscope + "." + RTLIL::unescape_id(wire->name)).c_str(), RTLIL::unescape_id(m->name).c_str()); + (iscope + "." + RTLIL::unescape_id(wire->name)).c_str(), log_id(m)); } t->fst_inputs[wire] = id; }