From e44fcbe19c891500384e3c06ceedaed697d7b717 Mon Sep 17 00:00:00 2001 From: George Rennie Date: Tue, 15 Jul 2025 12:26:19 +0100 Subject: [PATCH] kernel: remove $barrier from cellaigs and satgen * this was added earlier in the PR with the intention of making equiv_opt work, but it means barriers are lost through passes like aigmap and can potentially be used in optimization passes so it is better to remove it --- kernel/cellaigs.cc | 2 +- kernel/satgen.cc | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/kernel/cellaigs.cc b/kernel/cellaigs.cc index 0dee997ca..ce351514b 100644 --- a/kernel/cellaigs.cc +++ b/kernel/cellaigs.cc @@ -302,7 +302,7 @@ Aig::Aig(Cell *cell) } } - if (cell->type.in(ID($not), ID($_NOT_), ID($pos), ID($buf), ID($barrier), ID($_BUF_))) + if (cell->type.in(ID($not), ID($_NOT_), ID($pos), ID($buf), ID($_BUF_))) { for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) { int A = mk.inport(ID::A, i); diff --git a/kernel/satgen.cc b/kernel/satgen.cc index c1e0158af..437332613 100644 --- a/kernel/satgen.cc +++ b/kernel/satgen.cc @@ -431,7 +431,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) return true; } - if (cell->type.in(ID($pos), ID($buf), ID($barrier), ID($neg))) + if (cell->type.in(ID($pos), ID($buf), ID($neg))) { std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); @@ -439,7 +439,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) std::vector yy = model_undef ? ez->vec_var(y.size()) : y; - if (cell->type.in(ID($pos), ID($buf), ID($barrier))) { + if (cell->type.in(ID($pos), ID($buf))) { ez->assume(ez->vec_eq(a, yy)); } else { std::vector zero(a.size(), ez->CONST_FALSE); @@ -452,7 +452,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); extendSignalWidthUnary(undef_a, undef_y, cell); - if (cell->type.in(ID($pos), ID($buf), ID($barrier))) { + if (cell->type.in(ID($pos), ID($buf))) { ez->assume(ez->vec_eq(undef_a, undef_y)); } else { int undef_any_a = ez->expression(ezSAT::OpOr, undef_a);