From d7aca59e27f890e2b6d529774820978d04a39fbe Mon Sep 17 00:00:00 2001 From: AdvaySingh1 Date: Fri, 30 Jan 2026 11:22:00 -0800 Subject: [PATCH 01/23] Updated abc.cc and blifparse.cc --- abc | 2 +- frontends/blif/blifparse.cc | 65 ++++++++++++------- passes/techmap/abc.cc | 121 +++++++++++++++++++++++++++++------- 3 files changed, 143 insertions(+), 45 deletions(-) diff --git a/abc b/abc index 9dcae29da..85aa7f0b5 160000 --- a/abc +++ b/abc @@ -1 +1 @@ -Subproject commit 9dcae29da366ba9b7b518a8426545811be1ea61e +Subproject commit 85aa7f0b5c61532d8844882ddffa2a0e9f80d005 diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index 88ef6db88..da1f5e61a 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -249,6 +249,50 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool blif_maxnum = 0; } + // Check for .node_retention_begin after .end + if (read_next_line(buffer, buffer_size, line_count, f)) { + char *next_cmd = strtok(buffer, " \t\r\n"); + if (next_cmd != nullptr && !strcmp(next_cmd, ".node_retention_begin")) { + // Parse node retention information + while (read_next_line(buffer, buffer_size, line_count, f)) { + char *line_cmd = strtok(buffer, " \t\r\n"); + if (line_cmd == nullptr) + continue; + + // Check for end marker + if (!strcmp(line_cmd, ".node_retention_end")) + break; + + // Parse: node_name SRC source1 source2 ... + std::string node_name = line_cmd; + char *src_token = strtok(NULL, " \t\r\n"); + if (src_token == nullptr || strcmp(src_token, "SRC")) + continue; + + // Collect all source nodes + std::string sources; + char *source_token; + bool first = true; + while ((source_token = strtok(NULL, " \t\r\n")) != NULL) { + if (!first) + sources += " "; + sources += source_token; + first = false; + } + + // Find wire and set attribute + IdString wire_id = RTLIL::escape_id(node_name); + Wire *wire = module->wire(wire_id); + if (wire != nullptr && !sources.empty()) { + wire->attributes[RTLIL::IdString("\\node_retention_sources")] = Const(sources); + } + } + } else { + // Not .node_retention_begin, process this line normally + goto continue_without_read; + } + } + module = nullptr; lastcell = nullptr; obj_attributes = nullptr; @@ -470,27 +514,6 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool continue; } - if (!strcmp(cmd, ".gateinit")) - { - char *p = strtok(NULL, " \t\r\n"); - if (p == NULL) - goto error; - - char *n = strtok(p, "="); - char *init = strtok(NULL, "="); - if (n == NULL || init == NULL) - goto error; - if (init[0] != '0' && init[0] != '1') - goto error; - - if (blif_wire(n)->attributes.find(ID::init) == blif_wire(n)->attributes.end()) - blif_wire(n)->attributes.emplace(ID::init, Const(init[0] == '1' ? 1 : 0, 1)); - else - blif_wire(n)->attributes[ID::init] = Const(init[0] == '1' ? 1 : 0, 1); - - continue; - } - if (!strcmp(cmd, ".names")) { char *p; diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 6f958292d..4bacf2e40 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -29,6 +29,7 @@ // Kahn, Arthur B. (1962), "Topological sorting of large networks", Communications of the ACM 5 (11): 558-562, doi:10.1145/368996.369025 // http://en.wikipedia.org/wiki/Topological_sorting +#include #define ABC_COMMAND_LIB "strash; &get -n; &fraig -x; &put; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" #define ABC_COMMAND_CTR "strash; &get -n; &fraig -x; &put; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p" #define ABC_COMMAND_LUT "strash; &get -n; &fraig -x; &put; scorr; dc2; dretime; strash; dch -f; if; mfs2" @@ -142,6 +143,7 @@ struct AbcConfig bool map_mux8 = false; bool map_mux16 = false; bool markgroups = false; + bool read_blif_m = false; // Add -m flag to read_blif command pool enabled_gates; bool cmos_cost = false; int max_threads = -1; // -1 means auto (use number of modules) @@ -991,7 +993,8 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module log_header(design, "Extracting gate netlist of module `%s' to `%s/input.blif'..\n", module->name.c_str(), replace_tempdir(run_abc.tempdir_name, run_abc.tempdir_name, config.show_tempdir).c_str()); - std::string abc_script = stringf("read_blif \"%s/input.blif\"; ", run_abc.tempdir_name); + std::string abc_script = stringf("read_blif%s \"%s/input.blif\"; ", + config.read_blif_m ? " -m" : "", run_abc.tempdir_name); if (!config.liberty_files.empty() || !config.genlib_files.empty()) { std::string dont_use_args; @@ -1149,12 +1152,6 @@ bool read_until_abc_done(abc_output_filter &filt, int fd, DeferredLogs &logs) { // Ignore any leftover output, there should only be a prompt perhaps return true; } - // If ABC aborted the sourced script, it returns to the prompt and will - // never print YOSYS_ABC_DONE. Treat this as a failed run, not a hang. - if (line.substr(0, 7) == "Error: ") { - logs.log_error("ABC: %s", line.c_str()); - return false; - } filt.next_line(line); line.clear(); start = p + 1; @@ -1452,6 +1449,8 @@ void AbcModuleState::extract(AbcSigMap &assign_map, dict & ifs.close(); + IdString node_retention_id = RTLIL::IdString("\\node_retention_sources"); + log_header(design, "Re-integrating ABC results.\n"); RTLIL::Module *mapped_mod = mapped_design->module(ID(netlist)); if (mapped_mod == nullptr) @@ -1461,18 +1460,49 @@ void AbcModuleState::extract(AbcSigMap &assign_map, dict & for (auto w : mapped_mod->wires()) { RTLIL::Wire *orig_wire = nullptr; RTLIL::Wire *wire = module->addWire(remap_name(w->name, &orig_wire)); - if (orig_wire != nullptr && orig_wire->attributes.count(ID::src)) - wire->attributes[ID::src] = orig_wire->attributes[ID::src]; + // log("ABC REINTEGRATION: Processing wire: mapped_name=%s, orig_name=%s\n", + // w->name.c_str(), orig_wire ? orig_wire->name.c_str() : ""); + // if (orig_wire != nullptr && orig_wire->attributes.count(ID::src)) + // wire->attributes[ID::src] = orig_wire->attributes[ID::src]; // SILIMATE: Apply src attribute to the wire from the original wire - if (orig_wire != nullptr) { - if (sig2src.count(orig_sigmap(orig_wire))) { - wire->set_src_attribute(sig2src[orig_sigmap(orig_wire)]); - sig2src[mapped_sigmap(wire)] = wire->get_src_attribute(); - log_debug("Matched wire %s to driver attributes:\n", orig_wire->name.c_str()); - } else { - log_debug("No driver attributes found for wire %s\n", orig_wire->name.c_str()); + // TODO: remove + // if (orig_wire != nullptr) { + // if (sig2src.count(orig_sigmap(orig_wire))) { + // wire->set_src_attribute(sig2src[orig_sigmap(orig_wire)]); + // sig2src[mapped_sigmap(wire)] = wire->get_src_attribute(); + // // log("ABC REINTEGRATION: Matched wire %s to driver attributes\n", orig_wire->name.c_str()); + // // log("ABC REINTEGRATION: Source attribute = %s\n", wire->get_src_attribute().c_str()); + // } else { + // // log("ABC REINTEGRATION: No driver attributes found for wire %s\n", orig_wire->name.c_str()); + // } + // } + // END TODO + + // Add node retention sources to source attribute pool + if (w->attributes.count(node_retention_id)) { + std::string sources_str = w->attributes.at(node_retention_id).decode_string(); + // log("ABC REINTEGRATION: Node retention sources for wire %s = %s\n", w->name.c_str(), sources_str.c_str()); + pool src_pool; + std::istringstream src_stream(sources_str); + std::string src_node; + // log("About to check sources\n"); + while (src_stream >> src_node) { + // log("Getting the original source attribute for wire %s\n", src_node.c_str()); + IdString src_id = RTLIL::escape_id(src_node); + src_node = remap_name(src_id, &orig_wire); + // log("Printing the original name %s\n", src_node.c_str()); + if (orig_wire != nullptr) { + // log("Printing the original source attribute %s\n", orig_wire->get_src_attribute().c_str()); + // log("Printing the original source attribute 2 %s\n", sig2src[orig_sigmap(orig_wire)]); + src_pool.insert(sig2src[orig_sigmap(orig_wire)]); + src_pool.insert(orig_wire->get_src_attribute().c_str()); + } else { + log("WARNING: Source wire not found"); + // log("WARNING: Source wire not found 2 %s\n", w->name.c_str()); + } } + wire->add_strpool_attribute(ID::src, src_pool); } if (markgroups) wire->attributes[ID::abcgroup] = map_autoidx; @@ -1485,9 +1515,21 @@ void AbcModuleState::extract(AbcSigMap &assign_map, dict & for (auto c : mapped_mod->cells()) { // SILIMATE: set output port to either Y or Q depending on the cell's ports and apply src attribute to the driver cell - Wire *out_wire = c->getPort((c->hasPort(ID::Y)) ? ID::Y : ID::Q).as_wire(); - Wire *remapped_out_wire = module->wire(remap_name(out_wire->name)); - std::string src_attribute = sig2src[remapped_out_wire]; + log("Processing cell %s\n", c->name.c_str()); + pool src_pool; + if (c->hasPort(ID::Y) || c->hasPort(ID::Q)) { + Wire *out_wire = c->getPort((c->hasPort(ID::Y)) ? ID::Y : ID::Q).as_wire(); + Wire *remapped_out_wire = module->wire(remap_name(out_wire->name)); + if (remapped_out_wire != nullptr) { + src_pool = remapped_out_wire->get_strpool_attribute(ID::src); + log("For cell %s the output wire is %s\n", c->name.c_str(), remapped_out_wire->name.c_str()); + for (auto src : src_pool) { + log("The source for cell %s is %s\n", c->name.c_str(), src.c_str()); + } + } else { + log("Remapped cell output wire is nullptr for %s\n", c->name); + } + } if (builtin_lib) { @@ -1517,7 +1559,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, dict & RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name); cell->setPort(name, module->wire(remapped_name)); } - cell->set_src_attribute(src_attribute); // SILIMATE: set src attribute from wire + cell->add_strpool_attribute(ID::src, src_pool); // SILIMATE: set src attribute from wire pool cell->fixup_parameters(); // SILIMATE: fix up parameters design->select(module, cell); continue; @@ -1540,7 +1582,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, dict & RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name); cell->setPort(name, module->wire(remapped_name)); } - cell->set_src_attribute(src_attribute); // SILIMATE: set src attribute from wire + cell->add_strpool_attribute(ID::src, src_pool); // SILIMATE: set src attribute from wire pool cell->fixup_parameters(); // SILIMATE: fix up parameters design->select(module, cell); continue; @@ -1559,7 +1601,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, dict & RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name); cell->setPort(name, module->wire(remapped_name)); } - cell->set_src_attribute(src_attribute); // SILIMATE: set src attribute from wire + cell->add_strpool_attribute(ID::src, src_pool); // SILIMATE: set src attribute from wire pool cell->fixup_parameters(); // SILIMATE: fix up parameters design->select(module, cell); continue; @@ -1571,6 +1613,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, dict & RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name); cell->setPort(name, module->wire(remapped_name)); } + cell->add_strpool_attribute(ID::src, src_pool); // SILIMATE: set src attribute from wire pool design->select(module, cell); continue; } @@ -1581,6 +1624,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, dict & RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name); cell->setPort(name, module->wire(remapped_name)); } + cell->add_strpool_attribute(ID::src, src_pool); // SILIMATE: set src attribute from wire pool design->select(module, cell); continue; } @@ -1592,6 +1636,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, dict & RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name); cell->setPort(name, module->wire(remapped_name)); } + cell->add_strpool_attribute(ID::src, src_pool); // SILIMATE: set src attribute from wire pool design->select(module, cell); continue; } @@ -1602,6 +1647,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, dict & RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name); cell->setPort(name, module->wire(remapped_name)); } + cell->add_strpool_attribute(ID::src, src_pool); // SILIMATE: set src attribute from wire pool design->select(module, cell); continue; } @@ -1612,6 +1658,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, dict & RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name); cell->setPort(name, module->wire(remapped_name)); } + cell->add_strpool_attribute(ID::src, src_pool); // SILIMATE: set src attribute from wire pool design->select(module, cell); continue; } @@ -1652,6 +1699,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, dict & ff.sig_q = module->wire(remap_name(c->getPort(ID::Q).as_wire()->name)); RTLIL::Cell *cell = ff.emit(); if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx; + cell->add_strpool_attribute(ID::src, src_pool); // SILIMATE: set src attribute from wire pool design->select(module, cell); continue; } @@ -1701,6 +1749,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, dict & ff.sig_q = module->wire(remap_name(c->getPort(ID::Q).as_wire()->name)); RTLIL::Cell *cell = ff.emit(); if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx; + cell->add_strpool_attribute(ID::src, src_pool); // SILIMATE: set src attribute from wire pool design->select(module, cell); continue; } @@ -1725,7 +1774,8 @@ void AbcModuleState::extract(AbcSigMap &assign_map, dict & } cell->setPort(conn.first, newsig); } - design->select(module, cell); + cell->add_strpool_attribute(ID::src, src_pool); // SILIMATE: set src attribute from wire pool + } for (auto conn : mapped_mod->connections()) { @@ -1760,6 +1810,30 @@ void AbcModuleState::extract(AbcSigMap &assign_map, dict & log("ABC RESULTS: input signals: %8d\n", in_wires); log("ABC RESULTS: output signals: %8d\n", out_wires); + // Print source pool attributes for wires and cells + for (auto wire : module->wires()) { + pool src_pool = wire->get_strpool_attribute(ID::src); + if (!src_pool.empty()) { + std::string pool_str; + for (auto &s : src_pool) { + if (!pool_str.empty()) pool_str += " "; + pool_str += s; + } + // log("ABC REINTEGRATION: Wire %s src pool: %s\n", wire->name.c_str(), pool_str.c_str()); + } + } + for (auto cell : module->cells()) { + pool src_pool = cell->get_strpool_attribute(ID::src); + if (!src_pool.empty()) { + std::string pool_str; + for (auto &s : src_pool) { + if (!pool_str.empty()) pool_str += " "; + pool_str += s; + } + // log("ABC REINTEGRATION: Cell %s src pool: %s\n", cell->name.c_str(), pool_str.c_str()); + } + } + delete mapped_design; finish(); } @@ -2069,6 +2143,7 @@ struct AbcPass : public Pass { config.cleanup = !design->scratchpad_get_bool("abc.nocleanup", false); config.show_tempdir = design->scratchpad_get_bool("abc.showtmp", false); config.markgroups = design->scratchpad_get_bool("abc.markgroups", false); + config.read_blif_m = design->scratchpad_get_bool("abc.readblifm", false); config.max_threads = design->scratchpad_get_int("abc.max_threads", -1); config.reserved_cores = design->scratchpad_get_int("abc.reserved_cores", 4); From 3b4574b6486d4399f37193887a18217a4324b5e3 Mon Sep 17 00:00:00 2001 From: AdvaySingh1 Date: Fri, 30 Jan 2026 12:00:12 -0800 Subject: [PATCH 02/23] abc.cc node_retention pass cleanup --- passes/techmap/abc.cc | 57 +++---------------------------------------- 1 file changed, 3 insertions(+), 54 deletions(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 4bacf2e40..ea5caaa32 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1459,50 +1459,27 @@ void AbcModuleState::extract(AbcSigMap &assign_map, dict & bool markgroups = run_abc.config.markgroups; for (auto w : mapped_mod->wires()) { RTLIL::Wire *orig_wire = nullptr; - RTLIL::Wire *wire = module->addWire(remap_name(w->name, &orig_wire)); - // log("ABC REINTEGRATION: Processing wire: mapped_name=%s, orig_name=%s\n", - // w->name.c_str(), orig_wire ? orig_wire->name.c_str() : ""); - // if (orig_wire != nullptr && orig_wire->attributes.count(ID::src)) - // wire->attributes[ID::src] = orig_wire->attributes[ID::src]; - - // SILIMATE: Apply src attribute to the wire from the original wire - // TODO: remove - // if (orig_wire != nullptr) { - // if (sig2src.count(orig_sigmap(orig_wire))) { - // wire->set_src_attribute(sig2src[orig_sigmap(orig_wire)]); - // sig2src[mapped_sigmap(wire)] = wire->get_src_attribute(); - // // log("ABC REINTEGRATION: Matched wire %s to driver attributes\n", orig_wire->name.c_str()); - // // log("ABC REINTEGRATION: Source attribute = %s\n", wire->get_src_attribute().c_str()); - // } else { - // // log("ABC REINTEGRATION: No driver attributes found for wire %s\n", orig_wire->name.c_str()); - // } - // } - // END TODO + RTLIL::Wire *wire = module->addWire(remap_name(w->name)); // Add node retention sources to source attribute pool if (w->attributes.count(node_retention_id)) { std::string sources_str = w->attributes.at(node_retention_id).decode_string(); - // log("ABC REINTEGRATION: Node retention sources for wire %s = %s\n", w->name.c_str(), sources_str.c_str()); pool src_pool; std::istringstream src_stream(sources_str); std::string src_node; - // log("About to check sources\n"); while (src_stream >> src_node) { - // log("Getting the original source attribute for wire %s\n", src_node.c_str()); IdString src_id = RTLIL::escape_id(src_node); src_node = remap_name(src_id, &orig_wire); - // log("Printing the original name %s\n", src_node.c_str()); if (orig_wire != nullptr) { - // log("Printing the original source attribute %s\n", orig_wire->get_src_attribute().c_str()); - // log("Printing the original source attribute 2 %s\n", sig2src[orig_sigmap(orig_wire)]); src_pool.insert(sig2src[orig_sigmap(orig_wire)]); src_pool.insert(orig_wire->get_src_attribute().c_str()); } else { log("WARNING: Source wire not found"); - // log("WARNING: Source wire not found 2 %s\n", w->name.c_str()); } } wire->add_strpool_attribute(ID::src, src_pool); + } else { + log("No node retention sources found for wire %s\n", w->name.c_str()); } if (markgroups) wire->attributes[ID::abcgroup] = map_autoidx; @@ -1522,10 +1499,6 @@ void AbcModuleState::extract(AbcSigMap &assign_map, dict & Wire *remapped_out_wire = module->wire(remap_name(out_wire->name)); if (remapped_out_wire != nullptr) { src_pool = remapped_out_wire->get_strpool_attribute(ID::src); - log("For cell %s the output wire is %s\n", c->name.c_str(), remapped_out_wire->name.c_str()); - for (auto src : src_pool) { - log("The source for cell %s is %s\n", c->name.c_str(), src.c_str()); - } } else { log("Remapped cell output wire is nullptr for %s\n", c->name); } @@ -1810,30 +1783,6 @@ void AbcModuleState::extract(AbcSigMap &assign_map, dict & log("ABC RESULTS: input signals: %8d\n", in_wires); log("ABC RESULTS: output signals: %8d\n", out_wires); - // Print source pool attributes for wires and cells - for (auto wire : module->wires()) { - pool src_pool = wire->get_strpool_attribute(ID::src); - if (!src_pool.empty()) { - std::string pool_str; - for (auto &s : src_pool) { - if (!pool_str.empty()) pool_str += " "; - pool_str += s; - } - // log("ABC REINTEGRATION: Wire %s src pool: %s\n", wire->name.c_str(), pool_str.c_str()); - } - } - for (auto cell : module->cells()) { - pool src_pool = cell->get_strpool_attribute(ID::src); - if (!src_pool.empty()) { - std::string pool_str; - for (auto &s : src_pool) { - if (!pool_str.empty()) pool_str += " "; - pool_str += s; - } - // log("ABC REINTEGRATION: Cell %s src pool: %s\n", cell->name.c_str(), pool_str.c_str()); - } - } - delete mapped_design; finish(); } From d7a3b4e3122b05ac7e0ee4b5278087c67c59ad54 Mon Sep 17 00:00:00 2001 From: AdvaySingh1 Date: Fri, 30 Jan 2026 12:42:55 -0800 Subject: [PATCH 03/23] Removed extraneous readblif knob from abc.cc --- passes/techmap/abc.cc | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index ea5caaa32..9af012a44 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -143,7 +143,6 @@ struct AbcConfig bool map_mux8 = false; bool map_mux16 = false; bool markgroups = false; - bool read_blif_m = false; // Add -m flag to read_blif command pool enabled_gates; bool cmos_cost = false; int max_threads = -1; // -1 means auto (use number of modules) @@ -993,8 +992,7 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module log_header(design, "Extracting gate netlist of module `%s' to `%s/input.blif'..\n", module->name.c_str(), replace_tempdir(run_abc.tempdir_name, run_abc.tempdir_name, config.show_tempdir).c_str()); - std::string abc_script = stringf("read_blif%s \"%s/input.blif\"; ", - config.read_blif_m ? " -m" : "", run_abc.tempdir_name); + std::string abc_script = stringf("read_blif \"%s/input.blif\"; ", run_abc.tempdir_name); if (!config.liberty_files.empty() || !config.genlib_files.empty()) { std::string dont_use_args; @@ -2092,7 +2090,6 @@ struct AbcPass : public Pass { config.cleanup = !design->scratchpad_get_bool("abc.nocleanup", false); config.show_tempdir = design->scratchpad_get_bool("abc.showtmp", false); config.markgroups = design->scratchpad_get_bool("abc.markgroups", false); - config.read_blif_m = design->scratchpad_get_bool("abc.readblifm", false); config.max_threads = design->scratchpad_get_int("abc.max_threads", -1); config.reserved_cores = design->scratchpad_get_int("abc.reserved_cores", 4); From 7dab62cb42b758ff1b9860eb1b9bbb7ac13d9da5 Mon Sep 17 00:00:00 2001 From: AdvaySingh1 Date: Fri, 30 Jan 2026 12:43:59 -0800 Subject: [PATCH 04/23] ABC cleanup --- abc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/abc b/abc index 85aa7f0b5..a4f6299dc 160000 --- a/abc +++ b/abc @@ -1 +1 @@ -Subproject commit 85aa7f0b5c61532d8844882ddffa2a0e9f80d005 +Subproject commit a4f6299dc4495abc6ec7e94764468942b2d1c00f From fc61433faa24f1fd6b1fa10a1b98be3a010e2191 Mon Sep 17 00:00:00 2001 From: AdvaySingh1 Date: Fri, 30 Jan 2026 13:11:36 -0800 Subject: [PATCH 05/23] Reducing verbosity for cell printing --- passes/techmap/abc.cc | 1 - 1 file changed, 1 deletion(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 9af012a44..1742cdd9d 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1490,7 +1490,6 @@ void AbcModuleState::extract(AbcSigMap &assign_map, dict & for (auto c : mapped_mod->cells()) { // SILIMATE: set output port to either Y or Q depending on the cell's ports and apply src attribute to the driver cell - log("Processing cell %s\n", c->name.c_str()); pool src_pool; if (c->hasPort(ID::Y) || c->hasPort(ID::Q)) { Wire *out_wire = c->getPort((c->hasPort(ID::Y)) ? ID::Y : ID::Q).as_wire(); From 625d2caeaf7676e454ce840611b06ed5ea1f7cb5 Mon Sep 17 00:00:00 2001 From: AdvaySingh1 Date: Mon, 2 Feb 2026 09:30:00 -0800 Subject: [PATCH 06/23] ABC: Stylistic abc fixes --- abc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/abc b/abc index 79010216c..da3457143 160000 --- a/abc +++ b/abc @@ -1 +1 @@ -Subproject commit 79010216cb87427dd7a0c8d38f156494221be006 +Subproject commit da3457143c09ddc9e3e8ae73f8d41c92f288daa1 From 15625f56ed77ef7db874a7c0528c45eaf5811aab Mon Sep 17 00:00:00 2001 From: AdvaySingh1 Date: Mon, 2 Feb 2026 10:08:41 -0800 Subject: [PATCH 07/23] Removed cmath arbitrary include --- passes/techmap/abc.cc | 1 - 1 file changed, 1 deletion(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 1742cdd9d..522339874 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -29,7 +29,6 @@ // Kahn, Arthur B. (1962), "Topological sorting of large networks", Communications of the ACM 5 (11): 558-562, doi:10.1145/368996.369025 // http://en.wikipedia.org/wiki/Topological_sorting -#include #define ABC_COMMAND_LIB "strash; &get -n; &fraig -x; &put; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" #define ABC_COMMAND_CTR "strash; &get -n; &fraig -x; &put; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p" #define ABC_COMMAND_LUT "strash; &get -n; &fraig -x; &put; scorr; dc2; dretime; strash; dch -f; if; mfs2" From 964631909840a1a952954bbdfd545a48126007af Mon Sep 17 00:00:00 2001 From: AdvaySingh1 Date: Mon, 2 Feb 2026 10:10:01 -0800 Subject: [PATCH 08/23] Fixed source wire to be reset to nullptr so value isn't carried on --- passes/techmap/abc.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 522339874..d58851bd3 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1466,6 +1466,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, dict & std::string src_node; while (src_stream >> src_node) { IdString src_id = RTLIL::escape_id(src_node); + orig_wire = nullptr; src_node = remap_name(src_id, &orig_wire); if (orig_wire != nullptr) { src_pool.insert(sig2src[orig_sigmap(orig_wire)]); From b005f69e27ea6a35411416383b3437ac541bdf2a Mon Sep 17 00:00:00 2001 From: AdvaySingh1 Date: Mon, 2 Feb 2026 10:15:59 -0800 Subject: [PATCH 09/23] Added comments in blifparse.cc --- frontends/blif/blifparse.cc | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index da1f5e61a..4b7a08fd9 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -249,8 +249,12 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool blif_maxnum = 0; } - // Check for .node_retention_begin after .end - if (read_next_line(buffer, buffer_size, line_count, f)) { + // Parse optional node retention section that tracks signal source origins for ABC reintegration. + // Expected format: + // .node_retention_begin + // SRC [source2] ... + // .node_retention_end + if (read_next_line(buffer, buffer_size, line_count, f)) { char *next_cmd = strtok(buffer, " \t\r\n"); if (next_cmd != nullptr && !strcmp(next_cmd, ".node_retention_begin")) { // Parse node retention information @@ -267,7 +271,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool std::string node_name = line_cmd; char *src_token = strtok(NULL, " \t\r\n"); if (src_token == nullptr || strcmp(src_token, "SRC")) - continue; + continue; // Skip malformed lines missing "SRC" keyword // Collect all source nodes std::string sources; @@ -284,6 +288,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool IdString wire_id = RTLIL::escape_id(node_name); Wire *wire = module->wire(wire_id); if (wire != nullptr && !sources.empty()) { + // Store sources as attribute for abc.cc to propagate src annotations wire->attributes[RTLIL::IdString("\\node_retention_sources")] = Const(sources); } } From 900f8408af6f533bdd98c405fee2fea7eebb0c02 Mon Sep 17 00:00:00 2001 From: AdvaySingh1 Date: Mon, 2 Feb 2026 10:27:33 -0800 Subject: [PATCH 10/23] Fixed read_until_abc_done --- passes/techmap/abc.cc | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index d58851bd3..88d3ba1a9 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1149,6 +1149,12 @@ bool read_until_abc_done(abc_output_filter &filt, int fd, DeferredLogs &logs) { // Ignore any leftover output, there should only be a prompt perhaps return true; } + // If ABC aborted the sourced script, it returns to the prompt and will + // never print YOSYS_ABC_DONE. Treat this as a failed run, not a hang. + if (line.substr(0, 7) == "Error: ") { + logs.log_error("ABC: %s", line.c_str()); + return false; + } filt.next_line(line); line.clear(); start = p + 1; @@ -1157,6 +1163,7 @@ bool read_until_abc_done(abc_output_filter &filt, int fd, DeferredLogs &logs) { } } + void RunAbcState::run(ConcurrentStack &process_pool) { std::string buffer = stringf("%s/input.blif", tempdir_name); From 47469c2490c1a9fec0219cf74e0475c14d9ee23f Mon Sep 17 00:00:00 2001 From: AdvaySingh1 Date: Mon, 2 Feb 2026 10:32:32 -0800 Subject: [PATCH 11/23] Added re-added gateinit logic previously deleted --- frontends/blif/blifparse.cc | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index 4b7a08fd9..ca9b23c4f 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -519,6 +519,27 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool continue; } + if (!strcmp(cmd, ".gateinit")) + { + char *p = strtok(NULL, " \t\r\n"); + if (p == NULL) + goto error; + + char *n = strtok(p, "="); + char *init = strtok(NULL, "="); + if (n == NULL || init == NULL) + goto error; + if (init[0] != '0' && init[0] != '1') + goto error; + + if (blif_wire(n)->attributes.find(ID::init) == blif_wire(n)->attributes.end()) + blif_wire(n)->attributes.emplace(ID::init, Const(init[0] == '1' ? 1 : 0, 1)); + else + blif_wire(n)->attributes[ID::init] = Const(init[0] == '1' ? 1 : 0, 1); + + continue; + } + if (!strcmp(cmd, ".names")) { char *p; From f452702017d7abd0ab4e978f82f7c919aee316d5 Mon Sep 17 00:00:00 2001 From: AdvaySingh1 Date: Mon, 2 Feb 2026 12:08:18 -0800 Subject: [PATCH 12/23] Added abc.node_retention flag --- passes/techmap/abc.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 88d3ba1a9..4f9fb3a95 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -146,6 +146,7 @@ struct AbcConfig bool cmos_cost = false; int max_threads = -1; // -1 means auto (use number of modules) int reserved_cores = 4; // cores reserved for main thread and other work + bool abc_node_retention = false; // retain nodes in ABC (off by default) }; struct AbcSigVal { @@ -991,7 +992,7 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module log_header(design, "Extracting gate netlist of module `%s' to `%s/input.blif'..\n", module->name.c_str(), replace_tempdir(run_abc.tempdir_name, run_abc.tempdir_name, config.show_tempdir).c_str()); - std::string abc_script = stringf("read_blif \"%s/input.blif\"; ", run_abc.tempdir_name); + std::string abc_script = stringf("read_blif " + (config.abc_node_retention ? " -r" : "") + " \"%s/input.blif\"; ", run_abc.tempdir_name); if (!config.liberty_files.empty() || !config.genlib_files.empty()) { std::string dont_use_args; @@ -2084,7 +2085,7 @@ struct AbcPass : public Pass { config.map_mux16 = design->scratchpad_get_bool("abc.mux16", false); config.abc_dress = design->scratchpad_get_bool("abc.dress", false); g_arg = design->scratchpad_get_string("abc.g", g_arg); - + config.abc_node_retention = design->scratchpad_get_bool("abc.node_retention", false); config.fast_mode = design->scratchpad_get_bool("abc.fast", false); bool dff_mode = design->scratchpad_get_bool("abc.dff", false); std::string clk_str; From 07e21e763aeefb94eee0761d41d65e71ff48aeaa Mon Sep 17 00:00:00 2001 From: AdvaySingh1 Date: Mon, 2 Feb 2026 12:09:16 -0800 Subject: [PATCH 13/23] ABC: Refactored fEnabled flag --- abc | 2 +- passes/techmap/abc.cc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/abc b/abc index da3457143..0b06bc1ab 160000 --- a/abc +++ b/abc @@ -1 +1 @@ -Subproject commit da3457143c09ddc9e3e8ae73f8d41c92f288daa1 +Subproject commit 0b06bc1ab08186152de5f74e1a71674d9cdb974c diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 4f9fb3a95..3f284f844 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -992,7 +992,7 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module log_header(design, "Extracting gate netlist of module `%s' to `%s/input.blif'..\n", module->name.c_str(), replace_tempdir(run_abc.tempdir_name, run_abc.tempdir_name, config.show_tempdir).c_str()); - std::string abc_script = stringf("read_blif " + (config.abc_node_retention ? " -r" : "") + " \"%s/input.blif\"; ", run_abc.tempdir_name); + std::string abc_script = stringf((std::string("read_blif") + (config.abc_node_retention ? " -r" : "") + " \"%s/input.blif\"; ").c_str(), run_abc.tempdir_name); if (!config.liberty_files.empty() || !config.genlib_files.empty()) { std::string dont_use_args; From 1317cbbb62411f357485c8b0e859d4f91190108b Mon Sep 17 00:00:00 2001 From: AdvaySingh1 Date: Mon, 2 Feb 2026 14:13:18 -0800 Subject: [PATCH 14/23] ABC: Added r flag into Extra_UtilGetopt for IoCommandReadBlif --- abc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/abc b/abc index 0b06bc1ab..5b97cf78b 160000 --- a/abc +++ b/abc @@ -1 +1 @@ -Subproject commit 0b06bc1ab08186152de5f74e1a71674d9cdb974c +Subproject commit 5b97cf78bce5493bb84179e51f34d168eceafbfc From 2f3ed06b9ba62238d66af0207d841a6a13fc2c72 Mon Sep 17 00:00:00 2001 From: AdvaySingh1 Date: Mon, 2 Feb 2026 15:30:49 -0800 Subject: [PATCH 15/23] ABC: Added setify to reduce number of entries --- abc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/abc b/abc index 5b97cf78b..bc3288593 160000 --- a/abc +++ b/abc @@ -1 +1 @@ -Subproject commit 5b97cf78bce5493bb84179e51f34d168eceafbfc +Subproject commit bc32885936de2e4eded69843b19bf83ef18b784c From d097e536f26d7634dfed5e2edb7e586e7854ea33 Mon Sep 17 00:00:00 2001 From: AdvaySingh1 Date: Tue, 3 Feb 2026 08:33:57 -0800 Subject: [PATCH 16/23] Fixed log to log_error --- passes/techmap/abc.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 3f284f844..fd53a9193 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1485,7 +1485,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, dict & } wire->add_strpool_attribute(ID::src, src_pool); } else { - log("No node retention sources found for wire %s\n", w->name.c_str()); + log_error("No node retention sources found for wire %s\n", w->name.c_str()); } if (markgroups) wire->attributes[ID::abcgroup] = map_autoidx; From e73c15750cd5943cdb0ad82232af72e4d746fec4 Mon Sep 17 00:00:00 2001 From: Advay Singh <144560982+AdvaySingh1@users.noreply.github.com> Date: Tue, 3 Feb 2026 08:38:07 -0800 Subject: [PATCH 17/23] Update passes/techmap/abc.cc for WARNING: Source wire not Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com> --- passes/techmap/abc.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index fd53a9193..de551ba5f 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1480,7 +1480,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, dict & src_pool.insert(sig2src[orig_sigmap(orig_wire)]); src_pool.insert(orig_wire->get_src_attribute().c_str()); } else { - log("WARNING: Source wire not found"); + log("WARNING: Source wire not found for %s\n", src_node.c_str()); } } wire->add_strpool_attribute(ID::src, src_pool); From 941be57cae16ad00824b26a56d1b75d77c0896a7 Mon Sep 17 00:00:00 2001 From: Advay Singh <144560982+AdvaySingh1@users.noreply.github.com> Date: Tue, 3 Feb 2026 08:41:53 -0800 Subject: [PATCH 18/23] Added design->select after setting strpool_attribute for non-special case cells Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com> --- passes/techmap/abc.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index de551ba5f..bdf901014 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1753,7 +1753,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, dict & cell->setPort(conn.first, newsig); } cell->add_strpool_attribute(ID::src, src_pool); // SILIMATE: set src attribute from wire pool - + design->select(module, cell); } for (auto conn : mapped_mod->connections()) { From 0b960509339482f7b41a6ab329ad9438df44370c Mon Sep 17 00:00:00 2001 From: AdvaySingh1 Date: Tue, 3 Feb 2026 08:44:16 -0800 Subject: [PATCH 19/23] Added tabbing in blifparse to match sorroundings --- frontends/blif/blifparse.cc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index ca9b23c4f..a02aa65a2 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -249,12 +249,12 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool blif_maxnum = 0; } - // Parse optional node retention section that tracks signal source origins for ABC reintegration. - // Expected format: - // .node_retention_begin - // SRC [source2] ... - // .node_retention_end - if (read_next_line(buffer, buffer_size, line_count, f)) { + // Parse optional node retention section that tracks signal source origins for ABC reintegration. + // Expected format: + // .node_retention_begin + // SRC [source2] ... + // .node_retention_end + if (read_next_line(buffer, buffer_size, line_count, f)) { char *next_cmd = strtok(buffer, " \t\r\n"); if (next_cmd != nullptr && !strcmp(next_cmd, ".node_retention_begin")) { // Parse node retention information From 0e0740a3a0cb84d3b4fb57d2b831d1e3bbc17f7b Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Wed, 4 Feb 2026 00:08:42 -0800 Subject: [PATCH 20/23] Remove unnecessary blank line in abc.cc --- passes/techmap/abc.cc | 1 - 1 file changed, 1 deletion(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index bdf901014..48a287c92 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1164,7 +1164,6 @@ bool read_until_abc_done(abc_output_filter &filt, int fd, DeferredLogs &logs) { } } - void RunAbcState::run(ConcurrentStack &process_pool) { std::string buffer = stringf("%s/input.blif", tempdir_name); From 43027720d2aafc289508d3bb542a124327e70388 Mon Sep 17 00:00:00 2001 From: AdvaySingh1 Date: Wed, 4 Feb 2026 10:22:24 -0800 Subject: [PATCH 21/23] Fixed no sources log error to only output error if node_retention mode is on --- passes/techmap/abc.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 48a287c92..085d2e9db 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1483,7 +1483,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, dict & } } wire->add_strpool_attribute(ID::src, src_pool); - } else { + } else if (run_abc.config.abc_node_retention) { log_error("No node retention sources found for wire %s\n", w->name.c_str()); } From 16b5a8e350a36cc6464765190b334244ad57dcea Mon Sep 17 00:00:00 2001 From: AdvaySingh1 Date: Wed, 4 Feb 2026 12:02:31 -0800 Subject: [PATCH 22/23] ABC: added -M flag for nMaxOrigins --- abc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/abc b/abc index bc3288593..82fdc5a81 160000 --- a/abc +++ b/abc @@ -1 +1 @@ -Subproject commit bc32885936de2e4eded69843b19bf83ef18b784c +Subproject commit 82fdc5a81df8dcdd798eea56ecdc9f5a24f32813 From 607ef023395e7e4de2911c1d5bc6c2d34386adc2 Mon Sep 17 00:00:00 2001 From: AdvaySingh1 Date: Wed, 4 Feb 2026 12:03:55 -0800 Subject: [PATCH 23/23] Added abc_max_node_retention_origins flag in AbcConfig struct --- passes/techmap/abc.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 085d2e9db..5d1967f15 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -147,6 +147,7 @@ struct AbcConfig int max_threads = -1; // -1 means auto (use number of modules) int reserved_cores = 4; // cores reserved for main thread and other work bool abc_node_retention = false; // retain nodes in ABC (off by default) + int abc_max_node_retention_origins = 5; // number of node retention origins (default 5) }; struct AbcSigVal { @@ -992,7 +993,7 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module log_header(design, "Extracting gate netlist of module `%s' to `%s/input.blif'..\n", module->name.c_str(), replace_tempdir(run_abc.tempdir_name, run_abc.tempdir_name, config.show_tempdir).c_str()); - std::string abc_script = stringf((std::string("read_blif") + (config.abc_node_retention ? " -r" : "") + " \"%s/input.blif\"; ").c_str(), run_abc.tempdir_name); + std::string abc_script = stringf((std::string("read_blif") + (config.abc_node_retention ? stringf(" -M %d -r", config.abc_max_node_retention_origins) : "") + " \"%s/input.blif\"; ").c_str(), run_abc.tempdir_name); if (!config.liberty_files.empty() || !config.genlib_files.empty()) { std::string dont_use_args; @@ -2085,6 +2086,7 @@ struct AbcPass : public Pass { config.abc_dress = design->scratchpad_get_bool("abc.dress", false); g_arg = design->scratchpad_get_string("abc.g", g_arg); config.abc_node_retention = design->scratchpad_get_bool("abc.node_retention", false); + config.abc_max_node_retention_origins = design->scratchpad_get_int("abc.max_node_retention_origins", 5); config.fast_mode = design->scratchpad_get_bool("abc.fast", false); bool dff_mode = design->scratchpad_get_bool("abc.dff", false); std::string clk_str;