diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 488775d2c..4a16abee9 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -1822,7 +1822,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
 		return modname;
 
 	if (!quiet)
-		log_header(design, "Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", stripped_name.c_str());
+		log_header(design, "Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", stripped_name);
 	loadconfig();
 
 	pool<IdString> rewritten;
diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc
index 72ad8b2b7..80553347c 100644
--- a/frontends/liberty/liberty.cc
+++ b/frontends/liberty/liberty.cc
@@ -537,7 +537,7 @@ struct LibertyFrontend : public Frontend {
 		if (flag_wb && flag_lib)
 			log_error("-wb and -lib cannot be specified together!\n");
 
-		log_header(design, "Executing Liberty frontend: %s\n", filename.c_str());
+		log_header(design, "Executing Liberty frontend: %s\n", filename);
 
 		LibertyParser parser(*f, filename);
 		int cell_count = 0;
diff --git a/frontends/rpc/rpc_frontend.cc b/frontends/rpc/rpc_frontend.cc
index 80a6aae6d..625b2c0e8 100644
--- a/frontends/rpc/rpc_frontend.cc
+++ b/frontends/rpc/rpc_frontend.cc
@@ -163,7 +163,7 @@ struct RpcModule : RTLIL::Module {
 			stripped_name = stripped_name.substr(9);
 		log_assert(stripped_name[0] == '\\');
 
-		log_header(design, "Executing RPC frontend `%s' for module `%s'.\n", server->name.c_str(), stripped_name.c_str());
+		log_header(design, "Executing RPC frontend `%s' for module `%s'.\n", server->name, stripped_name);
 
 		std::string parameter_info;
 		for (auto &param : parameters) {
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 231891271..2bdaf40ce 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -485,7 +485,7 @@ struct VerilogFrontend : public Frontend {
 
 		extra_args(f, filename, args, argidx);
 
-		log_header(design, "Executing Verilog-2005 frontend: %s\n", filename.c_str());
+		log_header(design, "Executing Verilog-2005 frontend: %s\n", filename);
 
 		log("Parsing %s%s input from `%s' to AST representation.\n",
 				parse_mode.formal ? "formal " : "", parse_mode.sv ? "SystemVerilog" : "Verilog", filename.c_str());
diff --git a/kernel/register.cc b/kernel/register.cc
index 36e312968..fe67cc35c 100644
--- a/kernel/register.cc
+++ b/kernel/register.cc
@@ -199,7 +199,7 @@ void Pass::call(RTLIL::Design *design, std::string command)
 		while (!cmd_buf.empty() && (cmd_buf.back() == ' ' || cmd_buf.back() == '\t' ||
 				cmd_buf.back() == '\r' || cmd_buf.back() == '\n'))
 			cmd_buf.resize(cmd_buf.size()-1);
-		log_header(design, "Shell command: %s\n", cmd_buf.c_str());
+		log_header(design, "Shell command: %s\n", cmd_buf);
 		int retCode = run_command(cmd_buf);
 		if (retCode != 0)
 			log_cmd_error("Shell command returned error code %d.\n", retCode);
diff --git a/passes/cmds/exec.cc b/passes/cmds/exec.cc
index ff1ef11ff..ea82ff908 100644
--- a/passes/cmds/exec.cc
+++ b/passes/cmds/exec.cc
@@ -150,7 +150,7 @@ struct ExecPass : public Pass {
 			}
 		}
 
-		log_header(design, "Executing command \"%s\".\n", cmd.c_str());
+		log_header(design, "Executing command \"%s\".\n", cmd);
 		log_push();
 
 		fflush(stdout);
diff --git a/passes/cmds/logcmd.cc b/passes/cmds/logcmd.cc
index 57759fc90..dd2d708d8 100644
--- a/passes/cmds/logcmd.cc
+++ b/passes/cmds/logcmd.cc
@@ -107,7 +107,7 @@ struct LogPass : public Pass {
 		if (to_stderr) fprintf(stderr, "%s%s", text.c_str(), line_end);
 		if (to_log) {
 			if (!header) log("%s%s", text, line_end);
-			else log_header(design, "%s%s", text.c_str(), line_end);
+			else log_header(design, "%s%s", text, line_end);
 		}
 	}
 } LogPass;