diff --git a/kernel/newcelltypes.h b/kernel/newcelltypes.h
index 1c0a2c2db..df1c13960 100644
--- a/kernel/newcelltypes.h
+++ b/kernel/newcelltypes.h
@@ -415,7 +415,7 @@ static constexpr Categories categories;
 namespace Compat {
 	static constexpr auto internals_all = Categories::complement(categories.is_stdcell);
 	static constexpr auto internals_mem_ff = Categories::meet(categories.is_ff, categories.is_mem_noff);
-	// auto stdcells_mem = Categories::meet(internals_all, categories.is_mem_noff);
+	static constexpr auto stdcells_mem = Categories::meet(categories.is_stdcell, categories.is_mem_noff);
 };
 
 namespace {
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 86d96ea7a..97079ceca 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -20,6 +20,7 @@
 #include "kernel/register.h"
 #include "kernel/sigtools.h"
 #include "kernel/celltypes.h"
+#include "kernel/newcelltypes.h"
 #include "kernel/utils.h"
 #include "kernel/log.h"
 #include <stdlib.h>
@@ -31,7 +32,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 bool did_something;
 
-void replace_undriven(RTLIL::Module *module, const CellTypes &ct)
+void replace_undriven(RTLIL::Module *module, const NewCellTypes &ct)
 {
 	SigMap sigmap(module);
 	SigPool driven_signals;
@@ -409,9 +410,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 		}
 	}
 
-	CellTypes ct_memcells;
-	ct_memcells.setup_stdcells_mem();
-
 	if (!noclkinv)
 	for (auto cell : module->cells())
 	if (design->selected(module, cell)) {
@@ -435,7 +433,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 		if (cell->type.in(ID($dffe), ID($adffe), ID($aldffe), ID($sdffe), ID($sdffce), ID($dffsre), ID($dlatch), ID($adlatch), ID($dlatchsr)))
 			handle_polarity_inv(cell, ID::EN, ID::EN_POLARITY, assign_map, invert_map);
 
-		if (!ct_memcells.cell_known(cell->type))
+		if (!TurboCellTypes::Compat::stdcells_mem(cell->type))
 			continue;
 
 		handle_clkpol_celltype_swap(cell, "$_SR_N?_", "$_SR_P?_", ID::S, assign_map, invert_map);
@@ -2358,7 +2356,7 @@ struct OptExprPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		CellTypes ct(design);
+		NewCellTypes ct(design);
 		for (auto module : design->selected_modules())
 		{
 			log("Optimizing module %s.\n", log_id(module));