diff --git a/tests/abc_new/duplicate_cell_libs.ys b/tests/abc_new/duplicate_cell_libs.ys
index 351ead506..7590b04fb 100644
--- a/tests/abc_new/duplicate_cell_libs.ys
+++ b/tests/abc_new/duplicate_cell_libs.ys
@@ -1,6 +1,9 @@
 # https://github.com/YosysHQ/yosys/issues/4977
 
-# same cell name in two liberty files: abc asserts, should be an error (#4977)
+# abc names the duplicated cell before it asserts, which used to be lost in a
+# stdio buffer that the abort never flushed
+logger -expect log "There are two standard cells with the same name" 1
+logger -expect error "ABC" 1
 read_verilog <<EOT
 module top(input a, b, output y);
 	assign y = ~(a & b);
@@ -9,5 +12,6 @@ EOT
 
 hierarchy -top top
 techmap
+
+libcache -scl -disable
 abc_new -liberty openroad/cm_test_cells.lib -liberty dup_inv.lib
-select -assert-none t:$_*_
diff --git a/tests/abc_new/generate_mk.py b/tests/abc_new/generate_mk.py
index 58d0cfbab..f7d4a7230 100644
--- a/tests/abc_new/generate_mk.py
+++ b/tests/abc_new/generate_mk.py
@@ -8,7 +8,6 @@ import glob
 import gen_tests_makefile
 
 skip = [
-    "duplicate_cell_libs.ys",
     "hier_check.ys",
     "keep_wire.ys",
     "scopeinfo.ys",