From cd37b064f9e46a26ecc8d007e02e1891c2d7b895 Mon Sep 17 00:00:00 2001
From: Akash Levy <akash@silimate.com>
Date: Tue, 23 Sep 2025 01:07:41 -0700
Subject: [PATCH] Minor cleanup

---
 passes/cmds/trace.cc                |  2 +-
 passes/silimate/opt_balance_tree.cc |  2 +-
 passes/techmap/abc.cc               | 10 +++++-----
 passes/techmap/extract_reduce.cc    |  2 +-
 4 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/passes/cmds/trace.cc b/passes/cmds/trace.cc
index 1dcb7f41a..b374f16bd 100644
--- a/passes/cmds/trace.cc
+++ b/passes/cmds/trace.cc
@@ -150,7 +150,7 @@ struct DebugOnPass : public Pass {
 		log("Turn debug log messages on\n");
 		log("\n");
 	}
-	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	void execute(std::vector<std::string> args, RTLIL::Design *) override
 	{
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
diff --git a/passes/silimate/opt_balance_tree.cc b/passes/silimate/opt_balance_tree.cc
index 5c219f14d..e40728993 100644
--- a/passes/silimate/opt_balance_tree.cc
+++ b/passes/silimate/opt_balance_tree.cc
@@ -233,7 +233,7 @@ struct OptBalanceTreeWorker {
 						Cell* x = bfs_queue.front();
 						bfs_queue.pop_front();
 
-						for (auto port: {ID::A, ID::B}) {
+						for (IdString port: {ID::A, ID::B}) {
 							auto sig = sigmap(x->getPort(port));
 							Cell* drv = sig_to_driver[sig];
 							bool drv_ok = drv && is_right_type(drv, cell_type);
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 50f8bedd3..dbb6080e1 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -235,7 +235,7 @@ void AbcModuleState::mark_port(const AbcSigMap &assign_map, RTLIL::SigSpec sig)
 
 bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, bool keepff)
 {
-	if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
+	if (cell->is_builtin_ff()) {
 		FfData ff(&initvals, cell);
 		gate_type_t type = G(FF);
 		if (!ff.has_clk)
@@ -495,7 +495,7 @@ void AbcModuleState::dump_loop_graph(FILE *f, int &nr, dict<int, pool<int>> &edg
 	}
 
 	for (auto n : nodes)
-		fprintf(f, "  ys__n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, log_signal(signal_list[n].bit),
+		fprintf(f, "  ys__n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, log_signal(signal_list[n].bit).c_str(),
 				n, in_counts[n], workpool.count(n) ? ", shape=box" : "");
 
 	for (auto &e : edges)
@@ -611,7 +611,7 @@ void AbcModuleState::handle_loops(AbcSigMap &assign_map, RTLIL::Module *module)
 					log("Breaking loop using new signal %s: %s -> %s\n", log_signal(RTLIL::SigSpec(wire)),
 							log_signal(signal_list[id1].bit), log_signal(signal_list[id2].bit));
 				else
-					log("                               %*s  %s -> %s\n", int(strlen(log_signal(RTLIL::SigSpec(wire)))), "",
+					log("                               %*s  %s -> %s\n", int(strlen(log_signal(RTLIL::SigSpec(wire)).c_str())), "",
 							log_signal(signal_list[id1].bit), log_signal(signal_list[id2].bit));
 				first_line = false;
 			}
@@ -1014,7 +1014,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab
 	fprintf(f, "\n");
 
 	for (auto &si : signal_list)
-		fprintf(f, "# ys__n%-5d %s\n", si.id, log_signal(si.bit));
+		fprintf(f, "# ys__n%-5d %s\n", si.id, log_signal(si.bit).c_str());
 
 	for (auto &si : signal_list) {
 		if (si.bit.wire == nullptr) {
@@ -2282,7 +2282,7 @@ struct AbcPass : public Pass {
 					}
 				}
 
-				if (!RTLIL::builtin_ff_cell_types().count(cell->type))
+				if (!cell->is_builtin_ff())
 					continue;
 
 				FfData ff(&initvals, cell);
diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc
index fa9e62209..7fc852105 100644
--- a/passes/techmap/extract_reduce.cc
+++ b/passes/techmap/extract_reduce.cc
@@ -299,7 +299,7 @@ struct ExtractReducePass : public Pass
 						Cell* x = bfs_item.first;
 						SigBit excl = bfs_item.second;
 
-						for (auto port: {ID::B, ID::A}) {
+						for (IdString port: {ID::B, ID::A}) {
 							auto bit = sigmap(x->getPort(port)[0]);
 
 							bool sink_single = sig_to_sink[bit].size() == 1 && !port_sigs.count(bit);