From c783ccfdd6696d1da6c989e445be830f379122db Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 30 Sep 2026 12:59:01 +0200 Subject: [PATCH] read_verilog: fix sign extension in array pattern assignments --- frontends/ast/simplify.cc | 12 ++++++++++++ tests/svtypes/array_assign_pattern_signed.ys | 11 +++++++++++ 2 files changed, 23 insertions(+) create mode 100644 tests/svtypes/array_assign_pattern_signed.ys diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 2deec2698..fa15127ca 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1973,6 +1973,18 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin width_hint_here = -1, sign_hint_here = false; if (children_are_self_determined) width_hint_here = -1, sign_hint_here = false; + if (type == AST_ASSIGN_PATTERN) { + // It's unlikely for this simplify to run, but just to be sure + while (!children[i]->basic_prep && children[i]->simplify(false, stage, -1, false)) + did_something = true; + // Undo signedness inheritance of the children from the parent AST_ASSIGN_PATTERN + // but widen as needed + int child_width_hint; + bool child_sign_hint; + children[i]->detectSignWidth(child_width_hint, child_sign_hint); + width_hint_here = max(width_hint, child_width_hint); + sign_hint_here = child_sign_hint; + } did_something_here = children[i]->simplify(const_fold_here, stage, width_hint_here, sign_hint_here); if (did_something_here) did_something = true; diff --git a/tests/svtypes/array_assign_pattern_signed.ys b/tests/svtypes/array_assign_pattern_signed.ys new file mode 100644 index 000000000..26b59f8f3 --- /dev/null +++ b/tests/svtypes/array_assign_pattern_signed.ys @@ -0,0 +1,11 @@ +# Signed assignment pattern elements are sign-extended to the element width. +read_verilog -sv <>> 1}; + assign o0 = a[0]; + assign o1 = a[1]; +endmodule +EOT +proc +sat -verify -prove o0 16'hffff -prove o1 16'hfffc