From c75d80905a8e8e358e9604cf9823299d103d5dca Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Wed, 18 Feb 2026 21:20:13 +0100
Subject: [PATCH] modtools: fix database sanity on wire name swap

---
 kernel/modtools.h | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/kernel/modtools.h b/kernel/modtools.h
index 6dd7600e9..cf68693bc 100644
--- a/kernel/modtools.h
+++ b/kernel/modtools.h
@@ -28,6 +28,22 @@ YOSYS_NAMESPACE_BEGIN
 
 struct ModIndex : public RTLIL::Monitor
 {
+	struct PointerOrderedSigBit : public RTLIL::SigBit {
+		PointerOrderedSigBit(SigBit s) {
+			wire = s.wire;
+			if (wire)
+				offset = s.offset;
+			else
+				data = s.data;
+		}
+		inline bool operator<(const RTLIL::SigBit &other) const {
+			if (wire == other.wire)
+				return wire ? (offset < other.offset) : (data < other.data);
+			if (wire != nullptr && other.wire != nullptr)
+				return wire < other.wire; // look here
+			return (wire != nullptr) < (other.wire != nullptr);
+		}
+	};
 	struct PortInfo {
 		RTLIL::Cell* cell;
 		RTLIL::IdString port;
@@ -77,7 +93,7 @@ struct ModIndex : public RTLIL::Monitor
 
 	SigMap sigmap;
 	RTLIL::Module *module;
-	std::map<RTLIL::SigBit, SigBitInfo> database;
+	std::map<PointerOrderedSigBit, SigBitInfo> database;
 	int auto_reload_counter;
 	bool auto_reload_module;