From c55ee8399265950a69331ce02e68e0f4d28d7ed7 Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Thu, 8 May 2025 07:20:02 -0700 Subject: [PATCH] Add Design.run_pass API --- kernel/rtlil.cc | 6 ++++++ kernel/rtlil.h | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index f2433aace..f637cf0f7 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1254,6 +1254,12 @@ std::vector RTLIL::Design::selected_modules(RTLIL::SelectPartial return result; } +void RTLIL::Design::run_pass(std::string command) { + log("\n-- Running command `%s' --\n", command.c_str()); + Pass::call(this, command); + log_flush(); +} + RTLIL::Module::Module() { static unsigned int hashidx_count = 123456789; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index ef5e99bf6..18df82f41 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1446,6 +1446,10 @@ struct RTLIL::Design // returns all selected unboxed whole modules, warning the user if any // partially selected or boxed modules have been ignored std::vector selected_unboxed_whole_modules_warn() const { return selected_modules(SELECT_WHOLE_WARN, SB_UNBOXED_WARN); } + + // SILIMATE ADDED TO IMPROVE PYOSYS API + void run_pass(std::string command); + #ifdef WITH_PYTHON static std::map *get_all_designs(void); #endif