From 5c3c342ea01a2b95e8ee2d5b5691cd9da5dedaf8 Mon Sep 17 00:00:00 2001
From: Akash Levy <akash@silimate.com>
Date: Wed, 27 May 2026 00:09:12 -0700
Subject: [PATCH] Fixup NEW_ID usage

---
 passes/hierarchy/hierarchy.cc | 13 +++++++------
 passes/opt/opt_hier.cc        |  5 +++--
 2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 81c93c07b..72a7495c5 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -1416,7 +1416,7 @@ struct HierarchyPass : public Pass {
 							continue;
 						}
 
-						Wire *t = module->addWire(NEW_ID, GetSize(c));
+						Wire *t = module->addWire(NEW_ID2_SUFFIX("wand_wor"), GetSize(c));
 						new_sig.append(t);
 						update_port = true;
 
@@ -1440,24 +1440,25 @@ struct HierarchyPass : public Pass {
 			{
 				bool wand = wand_map.count(w);
 				SigSpec sigs = wand ? wand_map.at(w) : wor_map.at(w);
+				IdString name = w->name;
 
 				if (GetSize(sigs) == 0)
 					continue;
 
 				if (GetSize(w) == 1) {
 					if (wand)
-						module->addReduceAnd(NEW_ID, sigs, w);
+						module->addReduceAnd(NEW_ID4_SUFFIX("reduce_and"), sigs, w);
 					else
-						module->addReduceOr(NEW_ID, sigs, w);
+						module->addReduceOr(NEW_ID4_SUFFIX("reduce_or"), sigs, w);
 					continue;
 				}
 
 				SigSpec s = sigs.extract(0, GetSize(w));
 				for (int i = GetSize(w); i < GetSize(sigs); i += GetSize(w)) {
 					if (wand)
-						s = module->And(NEW_ID, s, sigs.extract(i, GetSize(w)));
+						s = module->And(NEW_ID4_SUFFIX("and"), s, sigs.extract(i, GetSize(w)));
 					else
-						s = module->Or(NEW_ID, s, sigs.extract(i, GetSize(w)));
+						s = module->Or(NEW_ID4_SUFFIX("or"), s, sigs.extract(i, GetSize(w)));
 				}
 				module->connect(w, s);
 			}
@@ -1519,7 +1520,7 @@ struct HierarchyPass : public Pass {
 							if (w->port_input && !w->port_output)
 								sig.extend_u0(GetSize(w), sig.is_wire() && sig.as_wire()->is_signed);
 							else
-								sig.append(module->addWire(NEW_ID, n));
+								sig.append(module->addWire(NEW_ID2_SUFFIX("port_resize"), n));
 						}
 
 						if (!conn.second.is_fully_const() || !w->port_input || w->port_output)
diff --git a/passes/opt/opt_hier.cc b/passes/opt/opt_hier.cc
index d8855ab56..b354bc434 100644
--- a/passes/opt/opt_hier.cc
+++ b/passes/opt/opt_hier.cc
@@ -94,6 +94,7 @@ struct ModuleIndex {
 
 	bool apply_changes(ModuleIndex &parent, Cell *instantiation) {
 		log_assert(instantiation->module == parent.module);
+		Cell *cell = instantiation;
 
 		if (module->get_blackbox_attribute()) {
 			// no propagating out of blackboxes
@@ -142,7 +143,7 @@ struct ModuleIndex {
 					rhs.replace(constant_outputs);
 					log_assert(rhs.is_fully_const());
 					parent.module->connect(value.extract(chunk.offset, chunk.width), rhs);
-					SigSpec dummy = parent.module->addWire(NEW_ID_SUFFIX("const_output"), chunk.width);
+					SigSpec dummy = parent.module->addWire(NEW_ID2_SUFFIX("const_output"), chunk.width);
 					for (int i = 0; i < chunk.width; i++)
 						value[chunk.offset + i] = dummy[i];
 				}
@@ -187,7 +188,7 @@ struct ModuleIndex {
 		severed_port_bits.sort_and_unify();
 		for (auto chunk : severed_port_bits.chunks()) {
 			SigSpec &value = instantiation->connections_.at(chunk.wire->name);
-			SigSpec dummy = parent.module->addWire(NEW_ID_SUFFIX("tie_together"), chunk.width);
+			SigSpec dummy = parent.module->addWire(NEW_ID2_SUFFIX("tie_together"), chunk.width);
 			for (int i = 0; i < chunk.width; i++)
 				value[chunk.offset + i] = dummy[i];
 		}