From c3c5388ed959903c6acee628ff2b03481c0ee89d Mon Sep 17 00:00:00 2001
From: nella <simontupy64@gmail.com>
Date: Sat, 19 Sep 2026 14:54:26 +0200
Subject: [PATCH] Clean up after bufnorm.

---
 backends/aiger2/aiger.cc     | 19 +++++++++++++++++++
 tests/abc_new/generate_mk.py | 14 +-------------
 tests/abc_new/hier_check.ys  |  7 +++++++
 3 files changed, 27 insertions(+), 13 deletions(-)

diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc
index 3f68e8df9..bddada5ae 100644
--- a/backends/aiger2/aiger.cc
+++ b/backends/aiger2/aiger.cc
@@ -1745,6 +1745,23 @@ struct XAigerWriter : AigerWriter {
 	}
 };
 
+// $input_port cells only encode buffer-normalized form, but bufNormalize(false)
+// leaves the cells in the design
+void remove_input_port_cells(Design *design)
+{
+	std::vector<Cell *> to_remove;
+
+	for (auto module : design->modules()) {
+		to_remove.clear();
+		for (auto cell : module->cells())
+			if (cell->type == ID($input_port))
+				to_remove.push_back(cell);
+
+		for (auto cell : to_remove)
+			module->remove(cell);
+	}
+}
+
 struct Aiger2Backend : Backend {
 	Aiger2Backend() : Backend("aiger2", "(experimental) write design to AIGER file")
 	{
@@ -1842,6 +1859,7 @@ struct Aiger2Backend : Backend {
 		// flag must not be kept on past the code that can work
 		// with it)
 		design->bufNormalize(false);
+		remove_input_port_cells(design);
 	}
 } Aiger2Backend;
 
@@ -1923,6 +1941,7 @@ struct XAiger2Backend : Backend {
 		// flag must not be kept on past the code that can work
 		// with it)
 		design->bufNormalize(false);
+		remove_input_port_cells(design);
 	}
 } XAiger2Backend;
 
diff --git a/tests/abc_new/generate_mk.py b/tests/abc_new/generate_mk.py
index f9de40bc7..6a921d5a0 100644
--- a/tests/abc_new/generate_mk.py
+++ b/tests/abc_new/generate_mk.py
@@ -3,18 +3,6 @@
 import sys
 sys.path.append("..")
 
-import glob
-
 import gen_tests_makefile
 
-skip = [
-    "hier_check.ys",
-]
-
-def create_tests():
-    for ys in sorted(glob.glob("*.ys")):
-        if ys in skip:
-            continue
-        gen_tests_makefile.generate_ys_test(ys)
-
-gen_tests_makefile.generate_custom(create_tests)
+gen_tests_makefile.generate(["--yosys-scripts"])
diff --git a/tests/abc_new/hier_check.ys b/tests/abc_new/hier_check.ys
index 711d41391..820c27bae 100644
--- a/tests/abc_new/hier_check.ys
+++ b/tests/abc_new/hier_check.ys
@@ -11,6 +11,13 @@ EOT
 
 hierarchy -top top
 techmap
+design -save pre
+
+abc9 -lut 4
+select -assert-none t:$input_port
+check -assert
+
+design -load pre
 abc_new -liberty openroad/cm_test_cells.lib
 select -assert-none t:$input_port
 check -assert