From c3a9a6d90e62e972a5757be6645ddbc059a39ec5 Mon Sep 17 00:00:00 2001 From: Stan Lee Date: Fri, 6 Mar 2026 09:59:51 -0800 Subject: [PATCH] fix --- passes/sat/sim.cc | 2 +- passes/silimate/reg_rename.cc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index eb3f39480..00b144037 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -1475,7 +1475,7 @@ struct SimWorker : SimShared fst = new FstData(sim_filename); timescale = fst->getTimescaleString(); if (scope.empty()) { - scopes = fst->autoScope(topmod); + std::vector scopes = fst->autoScope(topmod); if (scopes.empty()) { log_error("No scope found for module '%s'. Please specify -scope explicitly.\n", RTLIL::unescape_id(topmod->name).c_str()); diff --git a/passes/silimate/reg_rename.cc b/passes/silimate/reg_rename.cc index 05e5200fb..e5c7ffca2 100644 --- a/passes/silimate/reg_rename.cc +++ b/passes/silimate/reg_rename.cc @@ -200,7 +200,7 @@ struct RegRenamePass : public Pass { try { FstData fst(vcd_filename); if (scope.empty()) { - scopes = fst->autoScope(topmod); + std::vector scopes = fst.autoScope(topmod); if (scopes.empty()) { log_error("No scope found for module '%s'. Please specify -scope explicitly.\n", RTLIL::unescape_id(topmod->name).c_str());