From bbceaa6b5e50aecc5bf8e4ab0cc03ad4abccd966 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Tue, 14 Oct 2025 14:59:32 +1300
Subject: [PATCH] docs: Note partial support of modports

---
 docs/source/using_yosys/verilog.rst | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/docs/source/using_yosys/verilog.rst b/docs/source/using_yosys/verilog.rst
index 92f223e49..95c0168ba 100644
--- a/docs/source/using_yosys/verilog.rst
+++ b/docs/source/using_yosys/verilog.rst
@@ -370,7 +370,10 @@ from SystemVerilog:
 	- array literals are currently not supported
 
 - SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
-  ports are inputs or outputs are supported.
+  ports are inputs or outputs are supported when used with named arguments, but
+  not positional arguments.  i.e. ``driver_mod d0(.intf(intf0),
+  .in(inputs[0]));`` is supported but ``driver_mod d0(intf0, inputs[0]);`` is
+  not.
 
 - Assignments within expressions are supported.