diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 1f326cdee..91526ea23 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2655,7 +2655,7 @@ struct VerificExtNets } }; -std::string verific_import(Design *design, const std::map ¶meters, std::string top) +std::string verific_import(Design *design, const std::map ¶meters, std::string top, bool opt) { verific_sva_fsm_limit = 16; @@ -2767,6 +2767,44 @@ std::string verific_import(Design *design, const std::mapRemoveBuffers(); + + log(" Balancing timing for %s.\n", nl.first.c_str()); + unsigned result = nl.second->BalanceTiming(0); + log(" Balance timing result before: %d\n", result); + result = nl.second->BalanceTiming(1); + log(" Balance timing result after: %d\n", result); + + log(" Running post-elaboration for %s.\n", nl.first.c_str()); + nl.second->PostElaborationProcess(); + log(" Removing dangling logic for %s.\n", nl.first.c_str()); + nl.second->RemoveDanglingLogic(1, 1, 1); + + log(" Merging RAM write ports for %s.\n", nl.first.c_str()); + nl.second->MergeRamWritePorts(); + log(" Merging RAMs for %s.\n", nl.first.c_str()); + nl.second->MergeRams(); + + log(" Merging selectors for %s.\n", nl.first.c_str()); + nl.second->MergeSelectors(); + log(" Optimizing priority selectors for %s.\n", nl.first.c_str()); + nl.second->OptimizePrioSelectors(); + log(" Performing resource sharing for %s.\n", nl.first.c_str()); + nl.second->ResourceSharing(); + log(" Performing final resource merging for %s.\n", nl.first.c_str()); + nl.second->OptimizeSameInputSubstractorComparator(); + + log(" Balancing timing for %s.\n", nl.first.c_str()); + log(" Balance timing result before: %d\n", result); + result = nl.second->BalanceTiming(1); + log(" Balance timing result after: %d\n", result); + } + } + while (!nl_todo.empty()) { auto it = nl_todo.begin(); Netlist *nl = it->second; @@ -3201,8 +3239,11 @@ struct VerificPass : public Pass { RuntimeFlags::SetVar("db_preserve_user_nets", 1); RuntimeFlags::SetVar("db_preserve_x", 1); + RuntimeFlags::SetVar("db_merge_cascaded_muxes", 1); // SILIMATE: add to improve optimization + RuntimeFlags::SetVar("db_synopsys_register_names", 1); // SILIMATE: add to use Synopsys register names + RuntimeFlags::SetVar("db_allow_external_nets", 1); - RuntimeFlags::SetVar("db_infer_wide_operators", 1); + RuntimeFlags::SetVar("db_infer_wide_operators_post_elaboration", 1); // SILIMATE: infer post elaboration to improve optimization RuntimeFlags::SetVar("db_infer_set_reset_registers", 0); // Properly respect order of read and write for rams @@ -3384,7 +3425,8 @@ struct VerificPass : public Pass { break; } - if (GetSize(args) > argidx && (args[argidx] == "-auto_discover" || args[argidx] == "-hdl_sort")) + // SILIMATE: auto-discover + if (GetSize(args) > argidx && args[argidx] == "-auto_discover") { // Always operate in SystemVerilog mode unsigned verilog_mode = veri_file::SYSTEM_VERILOG; diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h index 0b9616e19..91947ca60 100644 --- a/frontends/verific/verific.h +++ b/frontends/verific/verific.h @@ -26,7 +26,7 @@ YOSYS_NAMESPACE_BEGIN extern int verific_verbose; extern bool verific_import_pending; -extern std::string verific_import(Design *design, const std::map ¶meters, std::string top = std::string()); +extern std::string verific_import(Design *design, const std::map ¶meters, std::string top = std::string(), bool opt = true); extern pool verific_sva_prims; diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 3ef04616f..b1f1d4888 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -794,6 +794,9 @@ struct HierarchyPass : public Pass { log(" -auto-top\n"); log(" automatically determine the top of the design hierarchy and mark it.\n"); log("\n"); + log(" -opt\n"); + log(" optimize all modules in design hierarchy.\n"); + log("\n"); log(" -chparam name value \n"); log(" elaborate the top module using this parameter value. Modules on which\n"); log(" this parameter does not exist may cause a warning message to be output.\n"); @@ -821,6 +824,7 @@ struct HierarchyPass : public Pass { { log_header(design, "Executing HIERARCHY pass (managing design hierarchy).\n"); + bool flag_opt = false; bool flag_check = false; bool flag_simcheck = false; bool flag_smtcheck = false; @@ -932,6 +936,10 @@ struct HierarchyPass : public Pass { auto_top_mode = true; continue; } + if (args[argidx] == "-opt") { + flag_opt = true; + continue; + } if (args[argidx] == "-chparam" && argidx+2 < args.size()) { const std::string &key = args[++argidx]; const std::string &value = args[++argidx]; @@ -981,7 +989,7 @@ struct HierarchyPass : public Pass { if (top_mod == nullptr && !load_top_mod.empty()) { #ifdef YOSYS_ENABLE_VERIFIC if (verific_import_pending) { - load_top_mod = verific_import(design, parameters, load_top_mod); + load_top_mod = verific_import(design, parameters, load_top_mod, flag_opt); top_mod = design->module(RTLIL::escape_id(load_top_mod)); } #endif @@ -990,7 +998,7 @@ struct HierarchyPass : public Pass { } else { #ifdef YOSYS_ENABLE_VERIFIC if (verific_import_pending) - verific_import(design, parameters); + verific_import(design, parameters, std::string(), flag_opt); #endif } diff --git a/verific b/verific index d34160e0d..ce8f924e5 160000 --- a/verific +++ b/verific @@ -1 +1 @@ -Subproject commit d34160e0db7adfe191bab15b0a59a4d5c676e33f +Subproject commit ce8f924e56aaf8b3b16156bdc28499c424d6f4b9