From b55fd6718b07f958bdfcd67f8ec4dfa346dba42f Mon Sep 17 00:00:00 2001 From: Lofty Date: Thu, 2 Apr 2026 10:47:08 +0100 Subject: [PATCH] write_xaiger2: fix indentation --- backends/aiger2/aiger.cc | 77 +++++++++++++++++++++------------------- 1 file changed, 40 insertions(+), 37 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 78aba4bee..96e1fe75f 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -177,6 +177,8 @@ struct Index { if (!strashing) { return (static_cast(this))->emit_gate(a, b); } else { + // AigMaker::node2index + if (a < b) std::swap(a, b); auto pair = std::make_pair(a, b); @@ -767,15 +769,15 @@ struct AigerWriter : Index { // populate inputs std::vector inputs; for (auto id : top->ports) { - Wire *w = top->wire(id); - log_assert(w); - if (w->port_input && !w->port_output) - for (int i = 0; i < w->width; i++) { - pi_literal(SigBit(w, i)) = lit_counter; - inputs.push_back(SigBit(w, i)); - lit_counter += 2; - ninputs++; - } + Wire *w = top->wire(id); + log_assert(w); + if (w->port_input && !w->port_output) + for (int i = 0; i < w->width; i++) { + pi_literal(SigBit(w, i)) = lit_counter; + inputs.push_back(SigBit(w, i)); + lit_counter += 2; + ninputs++; + } } this->f = f; @@ -783,27 +785,27 @@ struct AigerWriter : Index { write_header(); // insert padding where output literals will go (once known) for (auto id : top->ports) { - Wire *w = top->wire(id); - log_assert(w); - if (w->port_output) { - for (auto bit : SigSpec(w)) { - (void) bit; - char buf[16]; - snprintf(buf, sizeof(buf) - 1, "%08d\n", 0); - f->write(buf, strlen(buf)); - noutputs++; + Wire *w = top->wire(id); + log_assert(w); + if (w->port_output) { + for (auto bit : SigSpec(w)) { + (void) bit; + char buf[16]; + snprintf(buf, sizeof(buf) - 1, "%08d\n", 0); + f->write(buf, strlen(buf)); + noutputs++; + } } } - } auto data_start = f->tellp(); // now the guts std::vector> outputs; for (auto w : top->wires()) - if (w->port_output) { - for (auto bit : SigSpec(w)) - outputs.push_back({bit, eval_po(bit)}); - } + if (w->port_output) { + for (auto bit : SigSpec(w)) + outputs.push_back({bit, eval_po(bit)}); + } auto data_end = f->tellp(); // revisit header and the list of outputs @@ -908,33 +910,34 @@ struct XAigerAnalysis : Index { Wire *w = top->wire(id); log_assert(w); if (w->port_input && !w->port_output) - for (int i = 0; i < w->width; i++) - pi_literal(SigBit(w, i)) = 0; + for (int i = 0; i < w->width; i++) + pi_literal(SigBit(w, i)) = 0; } HierCursor cursor; for (auto box : top_minfo->found_blackboxes) { Module *def = design->module(box->type); if (!(def && def->has_attribute(ID::abc9_box_id))) - for (auto &conn : box->connections_) - if (box->port_dir(conn.first) != RTLIL::PD_INPUT) - for (auto bit : conn.second) - pi_literal(bit, &cursor) = 0; + for (auto &conn : box->connections_) + if (box->port_dir(conn.first) != RTLIL::PD_INPUT) + for (auto bit : conn.second) + pi_literal(bit, &cursor) = 0; } - for (auto w : top->wires()) - if (w->port_output) { - for (auto bit : SigSpec(w)) - (void) eval_po(bit); + for (auto w : top->wires()) { + if (w->port_output) { + for (auto bit : SigSpec(w)) + (void) eval_po(bit); + } } for (auto box : top_minfo->found_blackboxes) { Module *def = design->module(box->type); if (!(def && def->has_attribute(ID::abc9_box_id))) - for (auto &conn : box->connections_) - if (box->port_dir(conn.first) == RTLIL::PD_INPUT) - for (auto bit : conn.second) - (void) eval_po(bit); + for (auto &conn : box->connections_) + if (box->port_dir(conn.first) == RTLIL::PD_INPUT) + for (auto bit : conn.second) + (void) eval_po(bit); } } };