diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 81aa3f399..e7278b458 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -321,6 +321,16 @@ struct CellTypes
 		return it != cell_types.end() && it->second.inputs.count(port) != 0;
 	}
 
+	RTLIL::PortDir cell_port_dir(RTLIL::IdString type, RTLIL::IdString port) const
+	{
+		auto it = cell_types.find(type);
+		if (it == cell_types.end())
+			return RTLIL::PD_UNKNOWN;
+		bool is_input = it->second.inputs.count(port);
+		bool is_output = it->second.outputs.count(port);
+		return RTLIL::PortDir(is_input + is_output * 2);
+	}
+
 	bool cell_evaluable(RTLIL::IdString type) const
 	{
 		auto it = cell_types.find(type);
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 7cd6326fa..e0cdfeef1 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -4241,6 +4241,22 @@ bool RTLIL::Cell::output(const RTLIL::IdString& portname) const
 	return false;
 }
 
+RTLIL::PortDir RTLIL::Cell::port_dir(const RTLIL::IdString& portname) const
+{
+	if (yosys_celltypes.cell_known(type))
+		return yosys_celltypes.cell_port_dir(type, portname);
+	if (module && module->design) {
+		RTLIL::Module *m = module->design->module(type);
+		if (m == nullptr)
+			return PortDir::PD_UNKNOWN;
+		RTLIL::Wire *w = m->wire(portname);
+		if (w == nullptr)
+			return PortDir::PD_UNKNOWN;
+		return PortDir(w->port_input + w->port_output * 2);
+	}
+	return PortDir::PD_UNKNOWN;
+}
+
 bool RTLIL::Cell::hasParam(const RTLIL::IdString& paramname) const
 {
 	return parameters.count(paramname) != 0;
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index e0de79ea9..54d3227e4 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -83,6 +83,13 @@ namespace RTLIL
 		SB_EXCL_BB_CMDERR = 15 // call log_cmd_error on black boxed module
 	};
 
+	enum PortDir : unsigned char  {
+		PD_UNKNOWN = 0,
+		PD_INPUT = 1,
+		PD_OUTPUT = 2,
+		PD_INOUT = 3
+	};
+
 	struct Const;
 	struct AttrObject;
 	struct NamedObject;
@@ -1943,6 +1950,7 @@ public:
 	bool known() const;
 	bool input(const RTLIL::IdString &portname) const;
 	bool output(const RTLIL::IdString &portname) const;
+	PortDir port_dir(const RTLIL::IdString &portname) const;
 
 	// access cell parameters
 	bool hasParam(const RTLIL::IdString &paramname) const;