diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc
index 8c7ff58d9..3030ce074 100644
--- a/backends/rtlil/rtlil_backend.cc
+++ b/backends/rtlil/rtlil_backend.cc
@@ -523,6 +523,10 @@ struct RTLILBackend : public Backend {
 				stringify = true;
 				continue;
 			}
+			if (arg == "-resolve-src") {
+				stringify = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(f, filename, args, argidx);
@@ -597,6 +601,10 @@ struct DumpPass : public Pass {
 				stringify = true;
 				continue;
 			}
+			if (arg == "-resolve-src") {
+				stringify = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc
index 1517adf62..d05c7b61f 100644
--- a/frontends/liberty/liberty.cc
+++ b/frontends/liberty/liberty.cc
@@ -196,8 +196,8 @@ static RTLIL::SigSpec create_tristate(RTLIL::Module *module, RTLIL::SigSpec func
 
 static void create_latch_ff_wires(RTLIL::Module *module, const LibertyAst *node)
 {
-	module->addWire(Twine{RTLIL::escape_id(node->args.at(0))});
-	module->addWire(Twine{RTLIL::escape_id(node->args.at(1))});
+	module->addWire(module->design->twines.add(std::string{RTLIL::escape_id(node->args.at(0))}));
+	module->addWire(module->design->twines.add(std::string{RTLIL::escape_id(node->args.at(1))}));
 }
 
 static std::pair<RTLIL::SigSpec, RTLIL::SigSpec> find_latch_ff_wires(RTLIL::Module *module, const LibertyAst *node)
@@ -613,8 +613,8 @@ struct LibertyFrontend : public Frontend {
 			RTLIL::Module *module = new RTLIL::Module;
 			module->design = design;
 			std::string cell_name = RTLIL::escape_id(cell->args.at(0));
-			TwineRef cell_name_ref = TwineSearch(&design->twines).find(cell_name);
-			module->meta_->name = design->twines.add(Twine{cell_name});
+			TwineRef cell_name_ref = design->twines.add(std::string{cell_name});
+			module->meta_->name = cell_name_ref;
 
 			if (flag_lib)
 				module->set_bool_attribute(ID::blackbox);
@@ -647,7 +647,7 @@ struct LibertyFrontend : public Frontend {
 						}
 					}
 					if (!flag_lib || dir->value != "internal")
-						module->addWire(Twine{RTLIL::escape_id(node->args.at(0))});
+						module->addWire(module->design->twines.add(std::string{RTLIL::escape_id(node->args.at(0))}));
 				}
 
 				if (node->id == "bus" && node->args.size() == 1)
@@ -687,7 +687,7 @@ struct LibertyFrontend : public Frontend {
 					int bus_type_offset = std::get<1>(type_map.at(bus_type_node->value));
 					bool bus_type_upto = std::get<2>(type_map.at(bus_type_node->value));
 
-					Wire *wire = module->addWire(Twine{RTLIL::escape_id(node->args.at(0))}, bus_type_width);
+					Wire *wire = module->addWire(module->design->twines.add(std::string{RTLIL::escape_id(node->args.at(0))}), bus_type_width);
 					wire->start_offset = bus_type_offset;
 					wire->upto = bus_type_upto;
 
diff --git a/passes/cmds/autoname.cc b/passes/cmds/autoname.cc
index 02dbe3df4..6cbe4e6b4 100644
--- a/passes/cmds/autoname.cc
+++ b/passes/cmds/autoname.cc
@@ -48,7 +48,7 @@ int autoname_worker(Module *module, const dict<Wire*, unsigned int>& wire_score)
 				for (auto bit : conn.second)
 					if (bit.wire != nullptr && bit.wire->name[0] != '$') {
 						if (suffix.empty())
-							suffix = stringf("_%s_%s", cell->type.unescape(), module->design->twines.str(conn.first).c_str());
+							suffix = stringf("_%s_%s", cell->type.unescape(), module->design->twines.unescaped_str(conn.first).c_str());
 						name_proposal proposed_name(
 							bit.wire->name.str() + suffix,
 							cell->output(conn.first) ? 0 : wire_score.at(bit.wire)
@@ -66,7 +66,7 @@ int autoname_worker(Module *module, const dict<Wire*, unsigned int>& wire_score)
 				for (auto bit : conn.second)
 					if (bit.wire != nullptr && bit.wire->name[0] == '$' && !bit.wire->port_id) {
 						if (suffix.empty())
-							suffix = stringf("_%s", module->design->twines.str(conn.first).c_str());
+							suffix = stringf("_%s", module->design->twines.unescaped_str(conn.first).c_str());
 						name_proposal proposed_name(
 							cell->name.str() + suffix,
 							cell->output(conn.first) ? 0 : wire_score.at(bit.wire)
@@ -89,8 +89,8 @@ int autoname_worker(Module *module, const dict<Wire*, unsigned int>& wire_score)
 	for (auto &it : proposed_cell_names) {
 		if (best_name < it.second)
 			continue;
-		TwineRef n = module->uniquify(module->design->twines.add(Twine{it.second.name}));
-		log_debug("Rename cell %s in %s to %s.\n", it.first, module, module->design->twines.str(n).c_str());
+		TwineRef n = module->uniquify(module->design->twines.add(std::string{it.second.name}));
+		log_debug("Rename cell %s in %s to %s.\n", it.first, module, module->design->twines.unescaped_str(n).c_str());
 		module->rename(it.first, n);
 		count++;
 	}
@@ -98,8 +98,8 @@ int autoname_worker(Module *module, const dict<Wire*, unsigned int>& wire_score)
 	for (auto &it : proposed_wire_names) {
 		if (best_name < it.second)
 			continue;
-		TwineRef n = module->uniquify(module->design->twines.add(Twine{it.second.name}));
-		log_debug("Rename wire %s in %s to %s.\n", it.first, module, module->design->twines.str(n).c_str());
+		TwineRef n = module->uniquify(module->design->twines.add(std::string{it.second.name}));
+		log_debug("Rename wire %s in %s to %s.\n", it.first, module, module->design->twines.unescaped_str(n).c_str());
 		module->rename(it.first, n);
 		count++;
 	}
diff --git a/passes/cmds/box_derive.cc b/passes/cmds/box_derive.cc
index 0b920a521..62b0d0894 100644
--- a/passes/cmds/box_derive.cc
+++ b/passes/cmds/box_derive.cc
@@ -104,7 +104,7 @@ struct BoxDerivePass : Pass {
 					TwineRef derived_type = base->derive(d, cell->parameters);
 					Module *derived = d->module(derived_type);
 					log_assert(derived && "Failed to derive module\n");
-					log("derived %s\n", derived_type);
+					log("derived %s\n", d->twines.str(derived_type).c_str());
 
 					if (!naming_attr.empty() && derived->has_attribute(naming_attr)) {
 						IdString new_name = RTLIL::escape_id(derived->get_string_attribute(naming_attr));
diff --git a/passes/cmds/chtype.cc b/passes/cmds/chtype.cc
index b203d64a6..f8700d594 100644
--- a/passes/cmds/chtype.cc
+++ b/passes/cmds/chtype.cc
@@ -40,7 +40,7 @@ static void publish_design(RTLIL::Design* design) {
 		for (auto* cell : mod->cells()) {
 			IdString ct = cell->type;
 			if (ct.begins_with("$"))
-				cell->type_impl = cell->module->design->twines.add(Twine{"\\" + ct.str()});
+				cell->type_impl = cell->module->design->twines.add(std::string{"\\" + ct.str()});
 		}
 	}
 }
@@ -102,12 +102,12 @@ struct ChtypePass : public Pass {
 			for (auto cell : module->selected_cells())
 			{
 				if (map_types.count(cell->type)) {
-					cell->type_impl = cell->module->design->twines.add(Twine{map_types.at(cell->type).str()});
+					cell->type_impl = cell->module->design->twines.add(std::string{map_types.at(cell->type).str()});
 					continue;
 				}
 
 				if (set_type != IdString()) {
-					cell->type_impl = cell->module->design->twines.add(Twine{set_type.str()});
+					cell->type_impl = cell->module->design->twines.add(std::string{set_type.str()});
 					continue;
 				}
 			}
diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index ed4b1344f..644d6986b 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -42,7 +42,7 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std::
 
 	if (wire_to_rename != nullptr) {
 		log("Renaming wire %s to %s in module %s.\n", log_id(wire_to_rename), RTLIL::unescape_id(to_name), log_id(module));
-		module->rename(wire_to_rename, module->design->twines.add(Twine{to_name}));
+		module->rename(wire_to_rename, module->design->twines.add(std::string{to_name}));
 		if (wire_to_rename->port_id || flag_output) {
 			if (flag_output)
 				wire_to_rename->port_output = true;
@@ -55,7 +55,7 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std::
 		if (flag_output)
 			log_cmd_error("Called with -output but the specified object is a cell.\n");
 		log("Renaming cell %s to %s in module %s.\n", log_id(cell_to_rename), RTLIL::unescape_id(to_name), log_id(module));
-		module->rename(cell_to_rename, module->design->twines.add(Twine{to_name}));
+		module->rename(cell_to_rename, module->design->twines.add(std::string{to_name}));
 		return;
 	}
 
@@ -146,7 +146,7 @@ static bool rename_witness(RTLIL::Design *design, dict<RTLIL::Module *, int> &ca
 				for (auto &c : name)
 					if ((c < 'a' || c > 'z') && (c < 'A' || c > 'Z') && (c < '0' || c > '9') && c != '_')
 						c = '_';
-				auto new_id = ID(module->design->twines.str(module->uniquify(module->design->twines.add(Twine{"\\_witness_." + name}))));
+				auto new_id = IdString(module->design->twines.str(module->uniquify(module->design->twines.add(std::string{"\\_witness_." + name}))));
 				cell->set_hdlname_attribute({ "_witness_", strstr(new_id.c_str(), ".") + 1 });
 				renames.emplace_back(cell, new_id);
 			}
@@ -168,8 +168,8 @@ static bool rename_witness(RTLIL::Design *design, dict<RTLIL::Module *, int> &ca
 					for (auto &c : name)
 						if ((c < 'a' || c > 'z') && (c < 'A' || c > 'Z') && (c < '0' || c > '9') && c != '_')
 							c = '_';
-					auto new_id = ID(module->design->twines.str(module->uniquify(module->design->twines.add(Twine{"\\_witness_." + name}))));
-					auto new_wire = module->addWire(Twine{new_id.str()}, GetSize(sig_out));
+					auto new_id = IdString(module->design->twines.str(module->uniquify(module->design->twines.add(std::string{"\\_witness_." + name}))));
+					auto new_wire = module->addWire(module->design->twines.add(std::string{new_id.str()}), GetSize(sig_out));
 					new_wire->set_hdlname_attribute({ "_witness_", strstr(new_id.c_str(), ".") + 1 });
 					if (clk2fflogic)
 						module->connect({new_wire, sig_out});
@@ -190,13 +190,13 @@ static bool rename_witness(RTLIL::Design *design, dict<RTLIL::Module *, int> &ca
 			for (auto &c : name)
 				if ((c < 'a' || c > 'z') && (c < 'A' || c > 'Z') && (c < '0' || c > '9') && c != '_')
 					c = '_';
-			auto new_id = ID(module->design->twines.str(module->uniquify(module->design->twines.add(Twine{"\\_witness_." + name}))));
+			auto new_id = IdString(module->design->twines.str(module->uniquify(module->design->twines.add(std::string{"\\_witness_." + name}))));
 			renames.emplace_back(cell, new_id);
 			cell->set_hdlname_attribute({ "_witness_", strstr(new_id.c_str(), ".") + 1 });
 		}
 	}
 	for (auto rename : renames) {
-		module->rename(rename.first, module->design->twines.add(Twine{rename.second.str()}));
+		module->rename(rename.first, module->design->twines.add(std::string{rename.second.str()}));
 	}
 
 	cache[module] = has_witness_signals;
@@ -409,10 +409,10 @@ struct RenamePass : public Pass {
 						new_cell_names.emplace(cell, derive_name_from_src(cell->get_src_attribute(), counter++));
 
 				for (auto &it : new_wire_names)
-					module->rename(it.first, module->design->twines.add(Twine{it.second.str()}));
+					module->rename(it.first, module->design->twines.add(std::string{it.second.str()}));
 
 				for (auto &it : new_cell_names)
-					module->rename(it.first, module->design->twines.add(Twine{it.second.str()}));
+					module->rename(it.first, module->design->twines.add(std::string{it.second.str()}));
 			}
 		}
 		else
@@ -440,11 +440,10 @@ struct RenamePass : public Pass {
 									}
 								}
 							}
-							IdString new_wire_name_id = ID(found_wire->name.str() + wire_suffix);
-							module->rename(found_wire, module->design->twines.add(Twine{new_wire_name_id.str()}));
+							module->rename(found_wire, module->design->twines.add(std::string{found_wire->name.str() + wire_suffix}));
 						}
 					}
-					module->rename(cell, module->design->twines.add(Twine{new_name.str()}));
+					module->rename(cell, module->design->twines.add(std::string{new_name.str()}));
 				}
 			}
 		}
@@ -482,10 +481,10 @@ struct RenamePass : public Pass {
 					}
 
 				for (auto &it : new_wire_names)
-					module->rename(it.first, module->design->twines.add(Twine{it.second.str()}));
+					module->rename(it.first, module->design->twines.add(std::string{it.second.str()}));
 
 				for (auto &it : new_cell_names)
-					module->rename(it.first, module->design->twines.add(Twine{it.second.str()}));
+					module->rename(it.first, module->design->twines.add(std::string{it.second.str()}));
 			}
 		}
 		else
@@ -520,10 +519,10 @@ struct RenamePass : public Pass {
 						new_cell_names[cell] = NEW_ID;
 
 				for (auto &it : new_wire_names)
-					module->rename(it.first, module->design->twines.add(Twine{it.second.str()}));
+					module->rename(it.first, module->design->twines.add(std::string{it.second.str()}));
 
 				for (auto &it : new_cell_names)
-					module->rename(it.first, module->design->twines.add(Twine{it.second.str()}));
+					module->rename(it.first, module->design->twines.add(std::string{it.second.str()}));
 			}
 		}
 		else
@@ -532,7 +531,7 @@ struct RenamePass : public Pass {
 			if (argidx+1 != args.size())
 				log_cmd_error("Invalid number of arguments!\n");
 
-			TwineRef new_name = design->twines.add(Twine{RTLIL::escape_id(args[argidx])});
+			TwineRef new_name = design->twines.add(std::string{RTLIL::escape_id(args[argidx])});
 			RTLIL::Module *module = design->top_module();
 
 			if (module == nullptr)
@@ -571,10 +570,10 @@ struct RenamePass : public Pass {
 				}
 
 				for (auto &it : new_wire_names)
-					module->rename(it.first, module->design->twines.add(Twine{it.second.str()}));
+					module->rename(it.first, module->design->twines.add(std::string{it.second.str()}));
 
 				for (auto &it : new_cell_names)
-					module->rename(it.first, module->design->twines.add(Twine{it.second.str()}));
+					module->rename(it.first, module->design->twines.add(std::string{it.second.str()}));
 			}
 		}
 		else if (flag_unescape)
@@ -593,7 +592,7 @@ struct RenamePass : public Pass {
 					name = name.substr(1);
 					if (!VERILOG_BACKEND::id_is_verilog_escaped(name))
 						continue;
-					new_wire_names[wire] = ID(module->design->twines.str(module->uniquify(module->design->twines.add(Twine{"\\" + renamed_unescaped(name)}))));
+					new_wire_names[wire] = IdString(module->design->twines.str(module->uniquify(module->design->twines.add(std::string{"\\" + renamed_unescaped(name)}))));
 					auto new_name = new_wire_names[wire].str().substr(1);
 					if (VERILOG_BACKEND::id_is_verilog_escaped(new_name))
 						log_error("Failed to rename wire %s -> %s\n", name, new_name);
@@ -606,17 +605,17 @@ struct RenamePass : public Pass {
 					name = name.substr(1);
 					if (!VERILOG_BACKEND::id_is_verilog_escaped(name))
 						continue;
-					new_cell_names[cell] = ID(module->design->twines.str(module->uniquify(module->design->twines.add(Twine{"\\" + renamed_unescaped(name)}))));
+					new_cell_names[cell] = IdString(module->design->twines.str(module->uniquify(module->design->twines.add(std::string{"\\" + renamed_unescaped(name)}))));
 					auto new_name = new_cell_names[cell].str().substr(1);
 					if (VERILOG_BACKEND::id_is_verilog_escaped(new_name))
 						log_error("Failed to rename cell %s -> %s\n", name, new_name);
 				}
 
 				for (auto &it : new_wire_names)
-					module->rename(it.first, module->design->twines.add(Twine{it.second.str()}));
+					module->rename(it.first, module->design->twines.add(std::string{it.second.str()}));
 
 				for (auto &it : new_cell_names)
-					module->rename(it.first, module->design->twines.add(Twine{it.second.str()}));
+					module->rename(it.first, module->design->twines.add(std::string{it.second.str()}));
 
 				module->fixup_ports();
 			}
@@ -651,7 +650,7 @@ struct RenamePass : public Pass {
 				if (module_to_rename != nullptr) {
 					to_name = RTLIL::escape_id(to_name);
 					log("Renaming module %s to %s.\n", log_id(module_to_rename), to_name);
-					design->rename(module_to_rename, design->twines.add(Twine{to_name}));
+					design->rename(module_to_rename, design->twines.add(std::string{to_name}));
 				} else
 					log_cmd_error("Object `%s' not found!\n", from_name);
 			}
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index ec9270eb8..66c034e23 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -540,7 +540,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
 			}
 		}
 
-		auto twines = design->twines;
+		auto &twines = design->twines;
 		for (auto cell : mod->cells())
 		for (auto &conn : cell->connections())
 		{
@@ -549,9 +549,9 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
 				goto exclude_match;
 			for (auto &rule : rules) {
 				last_mode = rule.mode;
-				if (rule.cell_types.size() > 0 && rule.cell_types.count(twines.unescaped_str(cell->type_impl)) == 0)
+				if (rule.cell_types.size() > 0 && rule.cell_types.count(twines.str(cell->type_impl)) == 0)
 					continue;
-				if (rule.port_names.size() > 0 && rule.port_names.count(twines.unescaped_str(conn.first)) == 0)
+				if (rule.port_names.size() > 0 && rule.port_names.count(twines.str(conn.first)) == 0)
 					continue;
 				if (rule.mode == '+')
 					goto include_match;
@@ -1046,7 +1046,7 @@ static std::string describe_selection_for_assert(RTLIL::Design *design, RTLIL::S
 		if (whole_modules && sel->selected_whole_module(mod->name))
 			desc += stringf("%s\n", mod);
 		for (auto it : mod->selected_members())
-			desc += stringf("%s/%s\n", mod, it);
+			desc += stringf("%s/%s\n", mod, design->obj_name(it).c_str());
 	}
 	if (push_selection) design->pop_selection();
 	return desc;
diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc
index 4a7fe560b..4f632e7fe 100644
--- a/passes/cmds/stat.cc
+++ b/passes/cmds/stat.cc
@@ -517,7 +517,7 @@ struct statdata_t {
 		}
 	}
 
-	void log_data(TwineRef mod_name, bool top_mod, bool print_area = true, bool print_hierarchical = true, bool print_global_only = false)
+	void log_data(const std::string &mod_name, bool top_mod, bool print_area = true, bool print_hierarchical = true, bool print_global_only = false)
 	{
 
 		print_log_header(print_area, print_hierarchical, print_global_only);
@@ -558,7 +558,7 @@ struct statdata_t {
 		if (area != 0) {
 			log("\n");
 			if (print_hierarchical || print_global_only) {
-				log("   Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name, area);
+				log("   Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name.c_str(), area);
 				log("     of which used for sequential elements: %f (%.2f%%)\n", sequential_area, 100.0 * sequential_area / area);
 			} else {
 				double local_area = 0;
@@ -567,7 +567,7 @@ struct statdata_t {
 				double local_sequential_area = 0;
 				for (auto &it : local_seq_area_cells_by_type)
 					local_sequential_area += it.second;
-				log("   Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name, local_area);
+				log("   Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name.c_str(), local_area);
 				log("     of which used for sequential elements: %f (%.2f%%)\n", local_sequential_area,
 				    100.0 * local_sequential_area / local_area);
 			}
@@ -1028,7 +1028,7 @@ struct StatPass : public Pass {
 				log("\n");
 				log("=== %s%s ===\n", design->twines.unescaped_str(mod->name), mod->is_selected_whole() ? "" : " (partially selected)");
 				log("\n");
-				data.log_data(mod->name, false, has_area, hierarchy_mode);
+				data.log_data(design->twines.str(mod->name), false, has_area, hierarchy_mode);
 			}
 		}
 
@@ -1054,7 +1054,7 @@ struct StatPass : public Pass {
 				data.log_data_json("design", true, hierarchy_mode, true);
 			else if (GetSize(mod_stat) > 1) {
 				log("\n");
-				data.log_data(top_mod->name, true, has_area, hierarchy_mode, true);
+				data.log_data(design->twines.str(top_mod->name), true, has_area, hierarchy_mode, true);
 			}
 
 			design->scratchpad_set_int("stat.num_wires", data.num_wires);
diff --git a/passes/cmds/xprop.cc b/passes/cmds/xprop.cc
index 98cf9f8c1..5ebb761d3 100644
--- a/passes/cmds/xprop.cc
+++ b/passes/cmds/xprop.cc
@@ -982,8 +982,8 @@ struct XpropWorker
 				if (wire->port_input == wire->port_output) {
 					log_warning("Port %s not an input or an output port which is not supported by xprop\n", wire);
 				} else if ((options.split_inputs && !options.assume_def_inputs && wire->port_input) || (options.split_outputs && wire->port_output)) {
-					auto port_d = module->uniquify(Twine{module->design->twines.str(port) + "_d"});
-					auto port_x = module->uniquify(Twine{module->design->twines.str(port) + "_x"});
+					auto port_d = module->uniquify(module->design->twines.add(std::string{module->design->twines.str(port) + "_d"}));
+					auto port_x = module->uniquify(module->design->twines.add(std::string{module->design->twines.str(port) + "_x"}));
 
 					auto wire_d = module->addWire(port_d, GetSize(wire));
 					auto wire_x = module->addWire(port_x, GetSize(wire));
@@ -1036,8 +1036,8 @@ struct XpropWorker
 			int index_d = 0;
 			int index_x = 0;
 			std::string wname = module->design->twines.str(wire->name.ref());
-			auto name_d = module->uniquify(Twine{wname + "_d"}, index_d);
-			auto name_x = module->uniquify(Twine{wname + "_x"}, index_x);
+			auto name_d = module->uniquify(module->design->twines.add(std::string{wname + "_d"}), index_d);
+			auto name_x = module->uniquify(module->design->twines.add(std::string{wname + "_x"}), index_x);
 
 			auto hdlname = wire->get_hdlname_attribute();
 
diff --git a/passes/pmgen/generate.h b/passes/pmgen/generate.h
index 2e804b5ff..c42cdea8d 100644
--- a/passes/pmgen/generate.h
+++ b/passes/pmgen/generate.h
@@ -105,7 +105,7 @@ void generate_pattern(std::function<void(pm&,std::function<void()>)> run, const
 				cellcnt = GetSize(mod->cells());
 
 				if (found_match) {
-					Module *m = design->addModule(design->twines.add(Twine{stringf("\\pmtest_%s_%s_%05d",
+					Module *m = design->addModule(design->twines.add(std::string{stringf("\\pmtest_%s_%s_%05d",
 							pmclass, pattern, modcnt++)}));
 					log("Creating module %s with %d cells.\n", m, cellcnt);
 					mod->cloneInto(m);
@@ -126,7 +126,7 @@ void generate_pattern(std::function<void(pm&,std::function<void()>)> run, const
 		design->remove(mod);
 	}
 
-	Module *m = design->addModule(design->twines.add(Twine{stringf("\\pmtest_%s_%s", pmclass, pattern)}));
+	Module *m = design->addModule(design->twines.add(std::string{stringf("\\pmtest_%s_%s", pmclass, pattern)}));
 	log("Creating module %s with %d cells.\n", m, GetSize(mods));
 	for (auto mod : mods) {
 		Cell *c = m->addCell(mod->name, mod->name);
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index b38fe5ba4..258c734d5 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -1539,7 +1539,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
 
 	bool builtin_lib = run_abc.config.liberty_files.empty() && run_abc.config.genlib_files.empty();
 	RTLIL::Design *mapped_design = new RTLIL::Design;
-	parse_blif(mapped_design, ifs, builtin_lib ? TW(DFF) : TW(_dff_), false, run_abc.config.sop_mode);
+	parse_blif(mapped_design, ifs, builtin_lib ? TW::DFF : TW::_dff_, false, run_abc.config.sop_mode);
 
 	ifs.close();
 
@@ -1762,7 +1762,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
 			continue;
 		}
 
-		RTLIL::Cell *cell = module->addCell(rn(c->name), c->type_impl);
+		RTLIL::Cell *cell = module->addCell(rn(c->name), module->design->twines.copy_from(mapped_design->twines, c->type_impl));
 		if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
 		cell->parameters = c->parameters;
 		for (auto &conn : c->connections()) {
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 1c0201a8d..9b9cbd43d 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -718,7 +718,11 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 {
 	auto design = module->design;
 	log_assert(design);
-	auto refof = [&](RTLIL::IdString n) { return design->twines.add(std::string{n.str()}); };
+	// toposort keys cells by IdString; recover the cell's own pool ref rather
+	// than re-interning the flattened name, which would yield a fresh leaf that
+	// never matches a Suffix-shaped auto name.
+	dict<IdString, TwineRef> name_ref;
+	auto refof = [&](RTLIL::IdString n) { return name_ref.at(n); };
 
 	SigMap sigmap(module);
 
@@ -792,6 +796,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 					for (auto bit : sigmap(conn.second))
 						bit_drivers[bit].insert(cell->name);
 			}
+			name_ref[cell->name] = cell->name.ref();
 			toposort.node(cell->name);
 		}
 
@@ -1217,6 +1222,23 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
 	auto rn = [&](RTLIL::IdString n) { return design->twines.add(std::string{remap_name(n)}); };
 	auto refof = [&](RTLIL::IdString n) { return design->twines.add(std::string{n.str()}); };
 
+	dict<std::string, RTLIL::Wire*> module_wire_by_name;
+	for (auto w : module->wires())
+		module_wire_by_name[design->twines.str(w->name.ref())] = w;
+	auto wire_of = [&](TwineRef name) -> RTLIL::Wire* {
+		if (auto *w = module->wire(name)) return w;
+		auto it = module_wire_by_name.find(design->twines.str(name));
+		return it == module_wire_by_name.end() ? nullptr : it->second;
+	};
+	dict<std::string, RTLIL::Cell*> module_cell_by_name;
+	for (auto c : module->cells())
+		module_cell_by_name[design->twines.str(c->name.ref())] = c;
+	auto cell_of = [&](TwineRef name) -> RTLIL::Cell* {
+		if (auto *c = module->cell(name)) return c;
+		auto it = module_cell_by_name.find(design->twines.str(name));
+		return it == module_cell_by_name.end() ? nullptr : it->second;
+	};
+
 	RTLIL::Module *mapped_mod = design->module(design->twines.add(stringf("%s$abc9", module->name)));
 	if (mapped_mod == NULL)
 		log_error("ABC output file does not contain a module `%s$abc'.\n", module);
@@ -1398,7 +1420,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
 			}
 		}
 		else {
-			RTLIL::Cell *existing_cell = module->cell(mapped_cell->name.ref());
+			RTLIL::Cell *existing_cell = cell_of(mapped_cell->name.ref());
 			if (!existing_cell)
 				log_error("Cannot find existing box cell with name '%s' in original design.\n", mapped_cell);
 
@@ -1524,7 +1546,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
 	// Stitch in mapped_mod's inputs/outputs into module
 	for (auto port : mapped_mod->ports) {
 		RTLIL::Wire *mapped_wire = mapped_mod->wire(port);
-		RTLIL::Wire *wire = module->wire(port);
+		RTLIL::Wire *wire = wire_of(port);
 		log_assert(wire);
 
 		RTLIL::Wire *remap_wire = module->wire(rn(mapped_wire->name));
diff --git a/passes/techmap/clkbufmap.cc b/passes/techmap/clkbufmap.cc
index 1213cc398..505fa649f 100644
--- a/passes/techmap/clkbufmap.cc
+++ b/passes/techmap/clkbufmap.cc
@@ -125,12 +125,12 @@ struct ClkbufmapPass : public Pass {
 		// If true, use both ther -buf and -inpad cell for input ports that are clocks.
 		bool buffer_inputs = true;
 
-		TwineRef buf_celltype_ref = design->twines.add(Twine{RTLIL::escape_id(buf_celltype)});
-		TwineRef buf_portname_ref = design->twines.add(Twine{RTLIL::escape_id(buf_portname)});
-		TwineRef buf_portname2_ref = design->twines.add(Twine{RTLIL::escape_id(buf_portname2)});
-		TwineRef inpad_celltype_ref = design->twines.add(Twine{RTLIL::escape_id(inpad_celltype)});
-		TwineRef inpad_portname_ref = design->twines.add(Twine{RTLIL::escape_id(inpad_portname)});
-		TwineRef inpad_portname2_ref = design->twines.add(Twine{RTLIL::escape_id(inpad_portname2)});
+		TwineRef buf_celltype_ref = design->twines.add(std::string{RTLIL::escape_id(buf_celltype)});
+		TwineRef buf_portname_ref = design->twines.add(std::string{RTLIL::escape_id(buf_portname)});
+		TwineRef buf_portname2_ref = design->twines.add(std::string{RTLIL::escape_id(buf_portname2)});
+		TwineRef inpad_celltype_ref = design->twines.add(std::string{RTLIL::escape_id(inpad_celltype)});
+		TwineRef inpad_portname_ref = design->twines.add(std::string{RTLIL::escape_id(inpad_portname)});
+		TwineRef inpad_portname2_ref = design->twines.add(std::string{RTLIL::escape_id(inpad_portname2)});
 
 		Module *inpad_mod = design->module(inpad_celltype_ref);
 		if (inpad_mod) {
@@ -158,7 +158,7 @@ struct ClkbufmapPass : public Pass {
 							sink_ports.insert(make_pair(module->name.ref(), make_pair(wire->name.ref(), i)));
 					auto it = wire->attributes.find(ID::clkbuf_inv);
 					if (it != wire->attributes.end()) {
-						TwineRef in_name = design->twines.add(Twine{RTLIL::escape_id(it->second.decode_string())});
+						TwineRef in_name = design->twines.add(std::string{RTLIL::escape_id(it->second.decode_string())});
 						for (int i = 0; i < GetSize(wire); i++) {
 							inv_ports_out[make_pair(module->name.ref(), make_pair(wire->name.ref(), i))] = make_pair(in_name, i);
 							inv_ports_in[make_pair(module->name.ref(), make_pair(in_name, i))] = make_pair(wire->name.ref(), i);
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index 8a5af2e2b..f8f5ccab5 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -509,7 +509,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
 	}
 
 	auto &twines = module->design->twines;
-	auto conn_key = [&](char c) { return twines.add(Twine{std::string("\\") + c}); };
+	auto conn_key = [&](char c) { return twines.add(std::string{std::string("\\") + c}); };
 
 	std::map<std::string, int> stats;
 	for (auto cell : cell_list)
@@ -522,7 +522,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
 		module->remove(cell);
 
 		cell_mapping &cm = cell_mappings[cell_type];
-		RTLIL::Cell *new_cell = module->addCell(Twine{cell_name.str()}, twines.add(Twine{cm.cell_name.str()}));
+		RTLIL::Cell *new_cell = module->addCell(twines.add(std::string{cell_name.str()}), twines.add(std::string{cm.cell_name.str()}));
 
 		new_cell->set_src_attribute(twines.add(Twine{src}));
 
@@ -560,7 +560,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
 				sig = module->addWire(NEW_TWINE);
 			} else
 				log_abort();
-			new_cell->setPort(twines.add(Twine{"\\" + port.first}), sig);
+			new_cell->setPort(twines.add(std::string{"\\" + port.first}), sig);
 		}
 
 		stats[stringf("%s cells to %s cells", cell_type.c_str(), new_cell->type.unescape())]++;
diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc
index d8f71f32e..fd7f1204c 100644
--- a/passes/techmap/hilomap.cc
+++ b/passes/techmap/hilomap.cc
@@ -37,7 +37,7 @@ void hilomap_worker(RTLIL::SigSpec &sig)
 		if (bit == RTLIL::State::S1 && !hicell_celltype.empty()) {
 			if (!singleton_mode || last_hi == RTLIL::State::Sm) {
 				last_hi = module->addWire(NEW_TWINE);
-				RTLIL::Cell *cell = module->addCell(NEW_TWINE, Twine{RTLIL::escape_id(hicell_celltype)});
+				RTLIL::Cell *cell = module->addCell(NEW_TWINE, module->design->twines.add(std::string{RTLIL::escape_id(hicell_celltype)}));
 				cell->setPort(module->design->twines.add(std::string{RTLIL::escape_id(hicell_portname)}), last_hi);
 			}
 			bit = last_hi;
@@ -45,7 +45,7 @@ void hilomap_worker(RTLIL::SigSpec &sig)
 		if (bit == RTLIL::State::S0 && !locell_celltype.empty()) {
 			if (!singleton_mode || last_lo == RTLIL::State::Sm) {
 				last_lo = module->addWire(NEW_TWINE);
-				RTLIL::Cell *cell = module->addCell(NEW_TWINE, Twine{RTLIL::escape_id(locell_celltype)});
+				RTLIL::Cell *cell = module->addCell(NEW_TWINE, module->design->twines.add(std::string{RTLIL::escape_id(locell_celltype)}));
 				cell->setPort(module->design->twines.add(std::string{RTLIL::escape_id(locell_portname)}), last_lo);
 			}
 			bit = last_lo;
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index 032605535..8fa887091 100644
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -331,36 +331,36 @@ struct IopadmapPass : public Pass {
 
 							Cell *cell = module->addCell(
 								module->uniquify(Twine{stringf("$iopadmap$%s.%s[%d]", module, wire, i)}),
-								module->design->twines.add(Twine{RTLIL::escape_id(tinoutpad_celltype)}));
+								module->design->twines.add(std::string{RTLIL::escape_id(tinoutpad_celltype)}));
 
 							if (tinoutpad_neg_oe)
 								en_sig = module->NotGate(NEW_TWINE, en_sig);
-							cell->setPort(module->design->twines.add(Twine{RTLIL::escape_id(tinoutpad_portname_oe)}), en_sig);
+							cell->setPort(module->design->twines.add(std::string{RTLIL::escape_id(tinoutpad_portname_oe)}), en_sig);
 							cell->attributes[ID::keep] = RTLIL::Const(1);
 
 							if (tbuf_cell) {
 								module->remove(tbuf_cell);
-								cell->setPort(module->design->twines.add(Twine{RTLIL::escape_id(tinoutpad_portname_o)}), wire_bit);
-								cell->setPort(module->design->twines.add(Twine{RTLIL::escape_id(tinoutpad_portname_i)}), data_sig);
+								cell->setPort(module->design->twines.add(std::string{RTLIL::escape_id(tinoutpad_portname_o)}), wire_bit);
+								cell->setPort(module->design->twines.add(std::string{RTLIL::escape_id(tinoutpad_portname_i)}), data_sig);
 							} else if (is_driven) {
-								cell->setPort(module->design->twines.add(Twine{RTLIL::escape_id(tinoutpad_portname_i)}), wire_bit);
+								cell->setPort(module->design->twines.add(std::string{RTLIL::escape_id(tinoutpad_portname_i)}), wire_bit);
 							} else {
-								cell->setPort(module->design->twines.add(Twine{RTLIL::escape_id(tinoutpad_portname_o)}), wire_bit);
-								cell->setPort(module->design->twines.add(Twine{RTLIL::escape_id(tinoutpad_portname_i)}), data_sig);
+								cell->setPort(module->design->twines.add(std::string{RTLIL::escape_id(tinoutpad_portname_o)}), wire_bit);
+								cell->setPort(module->design->twines.add(std::string{RTLIL::escape_id(tinoutpad_portname_i)}), data_sig);
 							}
 							if (!tinoutpad_portname_pad.empty())
-								rewrite_bits[wire][i] = make_pair(cell, module->design->twines.add(Twine{RTLIL::escape_id(tinoutpad_portname_pad)}));
+								rewrite_bits[wire][i] = make_pair(cell, module->design->twines.add(std::string{RTLIL::escape_id(tinoutpad_portname_pad)}));
 						} else {
 							log("Mapping port %s.%s[%d] using %s.\n", module, wire, i, toutpad_celltype);
 
 							Cell *cell = module->addCell(
 								module->uniquify(Twine{stringf("$iopadmap$%s.%s[%d]", module, wire, i)}),
-								module->design->twines.add(Twine{RTLIL::escape_id(toutpad_celltype)}));
+								module->design->twines.add(std::string{RTLIL::escape_id(toutpad_celltype)}));
 
 							if (toutpad_neg_oe)
 								en_sig = module->NotGate(NEW_TWINE, en_sig);
-							cell->setPort(module->design->twines.add(Twine{RTLIL::escape_id(toutpad_portname_oe)}), en_sig);
-							cell->setPort(module->design->twines.add(Twine{RTLIL::escape_id(toutpad_portname_i)}), data_sig);
+							cell->setPort(module->design->twines.add(std::string{RTLIL::escape_id(toutpad_portname_oe)}), en_sig);
+							cell->setPort(module->design->twines.add(std::string{RTLIL::escape_id(toutpad_portname_i)}), data_sig);
 							cell->attributes[ID::keep] = RTLIL::Const(1);
 
 							if (tbuf_cell) {
@@ -368,7 +368,7 @@ struct IopadmapPass : public Pass {
 								module->connect(wire_bit, data_sig);
 							}
 							if (!toutpad_portname_pad.empty())
-								rewrite_bits[wire][i] = make_pair(cell, module->design->twines.add(Twine{RTLIL::escape_id(toutpad_portname_pad)}));
+								rewrite_bits[wire][i] = make_pair(cell, module->design->twines.add(std::string{RTLIL::escape_id(toutpad_portname_pad)}));
 						}
 						buf_ports.insert(make_pair(module->name.ref(), make_pair(wire->name.ref(), i)));
 					}
@@ -437,11 +437,11 @@ struct IopadmapPass : public Pass {
 
 						RTLIL::Cell *cell = module->addCell(
 							module->uniquify(Twine{stringf("$iopadmap$%s.%s", module->name.unescaped(), wire->name.unescaped())}),
-							module->design->twines.add(Twine{RTLIL::escape_id(celltype)}));
-						cell->setPort(module->design->twines.add(Twine{RTLIL::escape_id(portname_int)}), wire_bit);
+							module->design->twines.add(std::string{RTLIL::escape_id(celltype)}));
+						cell->setPort(module->design->twines.add(std::string{RTLIL::escape_id(portname_int)}), wire_bit);
 
 						if (!portname_pad.empty())
-							rewrite_bits[wire][i] = make_pair(cell, module->design->twines.add(Twine{RTLIL::escape_id(portname_pad)}));
+							rewrite_bits[wire][i] = make_pair(cell, module->design->twines.add(std::string{RTLIL::escape_id(portname_pad)}));
 						if (!widthparam.empty())
 							cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
 						if (!nameparam.empty())
@@ -453,8 +453,8 @@ struct IopadmapPass : public Pass {
 				{
 					RTLIL::Cell *cell = module->addCell(
 						module->uniquify(Twine{stringf("$iopadmap$%s.%s", module->name.unescaped(), wire->name.unescaped())}),
-						module->design->twines.add(Twine{RTLIL::escape_id(celltype)}));
-					cell->setPort(module->design->twines.add(Twine{RTLIL::escape_id(portname_int)}), RTLIL::SigSpec(wire));
+						module->design->twines.add(std::string{RTLIL::escape_id(celltype)}));
+					cell->setPort(module->design->twines.add(std::string{RTLIL::escape_id(portname_int)}), RTLIL::SigSpec(wire));
 
 					if (!portname_pad.empty()) {
 						RTLIL::Wire *new_wire = NULL;
@@ -463,7 +463,7 @@ struct IopadmapPass : public Pass {
 							wire);
 						module->swap_names(new_wire, wire);
 						wire->attributes.clear();
-						cell->setPort(module->design->twines.add(Twine{RTLIL::escape_id(portname_pad)}), RTLIL::SigSpec(new_wire));
+						cell->setPort(module->design->twines.add(std::string{RTLIL::escape_id(portname_pad)}), RTLIL::SigSpec(new_wire));
 					}
 					if (!widthparam.empty())
 						cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index eebb62b86..e924fc6a5 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -47,14 +47,27 @@ void apply_prefix(IdString prefix, IdString &id)
 		id = stringf("$techmap%s.%s", prefix, id);
 }
 
+TwineRef apply_prefix_ref(IdString prefix, IdString id, RTLIL::Design *design)
+{
+	std::string ids = id.str();
+	std::string shared, tail;
+	if (!ids.empty() && ids[0] == '\\') {
+		shared = prefix.str() + ".";
+		tail = ids.substr(1);
+	} else {
+		shared = "$techmap" + prefix.str() + ".";
+		tail = std::move(ids);
+	}
+	TwineRef pref = design->twines.add(std::move(shared));
+	return design->twines.add(Twine{Twine::Suffix{pref, std::move(tail)}});
+}
+
 void apply_prefix(IdString prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
 {
 	vector<SigChunk> chunks = sig;
 	for (auto &chunk : chunks)
 		if (chunk.wire != nullptr) {
-			IdString wire_name = chunk.wire->name;
-			apply_prefix(prefix, wire_name);
-			TwineRef wire_ref = module->design->twines.add(std::string{wire_name.str()});
+			TwineRef wire_ref = apply_prefix_ref(prefix, chunk.wire->name, module->design);
 			log_assert(module->wire(wire_ref) != nullptr);
 			chunk.wire = module->wire(wire_ref);
 		}
@@ -209,9 +222,7 @@ struct TechmapWorker
 							autopurge_tpl_bits.insert(bit);
 				}
 			}
-			IdString w_name = tpl_w->name;
-			apply_prefix(cell->name, w_name);
-			TwineRef w_ref = module->design->twines.add(std::string{w_name.str()});
+			TwineRef w_ref = apply_prefix_ref(cell->name, tpl_w->name, module->design);
 			RTLIL::Wire *w = module->wire(w_ref);
 			if (w != nullptr) {
 				temp_renamed_wires[w] = w->name.ref();
@@ -333,17 +344,18 @@ struct TechmapWorker
 			IdString c_name = tpl_cell->name;
 			bool techmap_replace_cell = c_name.ends_with("_TECHMAP_REPLACE_");
 
+			TwineRef c_ref;
 			if (techmap_replace_cell)
-				c_name = orig_cell_name;
+				c_ref = module->design->twines.add(std::string{orig_cell_name});
 			else if (const char *p = strstr(tpl_cell->name.str().c_str(), "_TECHMAP_REPLACE_."))
-				c_name = stringf("%s%s", orig_cell_name, p + strlen("_TECHMAP_REPLACE_"));
+				c_ref = module->design->twines.add(stringf("%s%s", orig_cell_name, p + strlen("_TECHMAP_REPLACE_")));
 			else
-				apply_prefix(cell->name, c_name);
+				c_ref = apply_prefix_ref(cell->name, tpl_cell->name, module->design);
 
-			RTLIL::Cell *c = module->addCell(module->design->twines.add(std::string{c_name.str()}), tpl_cell);
+			RTLIL::Cell *c = module->addCell(c_ref, tpl_cell);
 			design->select(module, c);
 
-			if (c->type.in(TwineRef{TW(_TECHMAP_PLACEHOLDER_)}) && tpl_cell->has_attribute(ID::techmap_chtype)) {
+			if (c->type.in(TW::_TECHMAP_PLACEHOLDER_) && tpl_cell->has_attribute(ID::techmap_chtype)) {
 				c->type_impl = module->design->twines.add(std::string{RTLIL::escape_id(tpl_cell->get_string_attribute(ID::techmap_chtype))});
 				c->attributes.erase(ID::techmap_chtype);
 			}
@@ -630,7 +642,7 @@ struct TechmapWorker
 				if (tpl->avail_parameters.count(ID::_TECHMAP_CELLTYPE_) != 0)
 					parameters.emplace(ID::_TECHMAP_CELLTYPE_, cell->type.unescaped());
 				if (tpl->avail_parameters.count(ID::_TECHMAP_CELLNAME_) != 0)
-					parameters.emplace(ID::_TECHMAP_CELLNAME_, cell->module->design->twines.str(cell->meta_->name));
+					parameters.emplace(ID::_TECHMAP_CELLNAME_, cell->module->design->twines.unescaped_str(cell->meta_->name));
 
 				for (auto &conn : cell->connections()) {
 					if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", design->twines.unescaped_str(conn.first))) != 0) {
diff --git a/passes/tests/raise_error.cc b/passes/tests/raise_error.cc
index 0a75f4d0e..4feec04d7 100644
--- a/passes/tests/raise_error.cc
+++ b/passes/tests/raise_error.cc
@@ -72,7 +72,7 @@ struct RaiseErrorPass : public Pass {
 		int err_no = 1;
 		string err_msg = "";
 		if (err_obj != nullptr) {
-			log("Raising error from '%s'.\n", err_obj);
+			log("Raising error from '%s'.\n", design->obj_name(err_obj).c_str());
 			err_no = err_obj->attributes[ID::raise_error].as_int();
 			if (err_no > 256) {
 				err_msg = err_obj->get_string_attribute(ID::raise_error);