diff --git a/tests/silimate/opt_balance_tree.ys b/tests/silimate/opt_balance_tree.ys
index 50795226a..ed683cb9b 100644
--- a/tests/silimate/opt_balance_tree.ys
+++ b/tests/silimate/opt_balance_tree.ys
@@ -127,7 +127,7 @@ module top (
   input wire b,
   input wire c,
   input wire d,
-  output wire [3:0] x,
+  output wire [3:0] x
 );
   assign x[0] = a & b;
   assign x[1] = x[0] & c;