From abc7563a35cf4f9927d19cd0f430ff6f6c606f94 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Wed, 18 Feb 2026 22:15:44 +0100
Subject: [PATCH] modtools: add ModIndex unit test

---
 kernel/modtools.h                 | 12 ++++++--
 tests/unit/kernel/modindexTest.cc | 47 +++++++++++++++++++++++++++++++
 2 files changed, 56 insertions(+), 3 deletions(-)
 create mode 100644 tests/unit/kernel/modindexTest.cc

diff --git a/kernel/modtools.h b/kernel/modtools.h
index cf68693bc..5cd8e3cb2 100644
--- a/kernel/modtools.h
+++ b/kernel/modtools.h
@@ -151,11 +151,11 @@ struct ModIndex : public RTLIL::Monitor
 		}
 	}
 
-	void check()
+	bool ok()
 	{
 #ifndef NDEBUG
 		if (auto_reload_module)
-			return;
+			return true;
 
 		for (auto it : database)
 			log_assert(it.first == sigmap(it.first));
@@ -175,11 +175,17 @@ struct ModIndex : public RTLIL::Monitor
 				else if (!(it.second == database_bak.at(it.first)))
 					log("ModuleIndex::check(): Different content for database[%s].\n", log_signal(it.first));
 
-			log_assert(database == database_bak);
+			return false;
 		}
+		return true;
 #endif
 	}
 
+	void check()
+	{
+		log_assert(ok());
+	}
+
 	void notify_connect(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
 	{
 		log_assert(module == cell->module);
diff --git a/tests/unit/kernel/modindexTest.cc b/tests/unit/kernel/modindexTest.cc
new file mode 100644
index 000000000..1921c9a93
--- /dev/null
+++ b/tests/unit/kernel/modindexTest.cc
@@ -0,0 +1,47 @@
+#include <gtest/gtest.h>
+
+#include "kernel/modtools.h"
+#include "kernel/rtlil.h"
+
+YOSYS_NAMESPACE_BEGIN
+
+TEST(ModIndexSwapTest, has)
+{
+    Design* d = new Design;
+    Module* m = d->addModule("$m");
+    Wire* o = m->addWire("$o", 2);
+    o->port_input = true;
+    Wire* i = m->addWire("$i", 2);
+    i->port_input = true;
+    m->fixup_ports();
+    m->addNot("$not", i, o);
+    auto mi = ModIndex(m);
+    mi.reload_module();
+    for (auto [sb, info] : mi.database) {
+        EXPECT_TRUE(mi.database.find(sb) != mi.database.end());
+    }
+    m->swap_names(i, o);
+    for (auto [sb, info] : mi.database) {
+        EXPECT_TRUE(mi.database.find(sb) != mi.database.end());
+    }
+}
+
+TEST(ModIndexDeleteTest, has)
+{
+    if (log_files.empty()) log_files.emplace_back(stdout);
+    Design* d = new Design;
+    Module* m = d->addModule("$m");
+    Wire* w = m->addWire("$w");
+    Wire* o = m->addWire("$o");
+    o->port_output = true;
+    m->fixup_ports();
+    Cell* not_ = m->addNotGate("$not", w, o);
+    auto mi = ModIndex(m);
+    mi.reload_module();
+    mi.dump_db();
+    Wire* a = m->addWire("\\a");
+    not_->setPort(ID::A, a);
+    EXPECT_TRUE(mi.ok());
+}
+
+YOSYS_NAMESPACE_END