From 70291f0e4954a81dfae5a236ecafda9abc43e5f7 Mon Sep 17 00:00:00 2001
From: George Rennie <georgerennie@gmail.com>
Date: Fri, 30 May 2025 14:25:35 +0100
Subject: [PATCH 1/2] read_verilog: fix -1 constant used to correct post
 increment/decrement

---
 frontends/verilog/verilog_parser.y | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 9d0956c8e..fa624d471 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -336,7 +336,8 @@ static AstNode *addIncOrDecExpr(AstNode *lhs, dict<IdString, AstNode*> *attr, AS
 	log_assert(stmt->type == AST_ASSIGN_EQ);
 	AstNode *expr = stmt->children[0]->clone();
 	if (undo) {
-		AstNode *minus_one = AstNode::mkconst_int(-1, true, 1);
+		AstNode *one = AstNode::mkconst_int(1, false, 1);
+		AstNode *minus_one = new AstNode(AST_NEG, one);
 		expr = new AstNode(op, expr, minus_one);
 	}
 	SET_AST_NODE_LOC(expr, begin, end);

From 3790be114f770b336b9aa815236504f8173870bd Mon Sep 17 00:00:00 2001
From: George Rennie <georgerennie@gmail.com>
Date: Fri, 30 May 2025 14:36:05 +0100
Subject: [PATCH 2/2] tests: add tests for verilog pre/post increment/decrement
 in expressions

---
 tests/verilog/incdec.ys | 68 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 68 insertions(+)
 create mode 100644 tests/verilog/incdec.ys

diff --git a/tests/verilog/incdec.ys b/tests/verilog/incdec.ys
new file mode 100644
index 000000000..9133061a5
--- /dev/null
+++ b/tests/verilog/incdec.ys
@@ -0,0 +1,68 @@
+# From https://github.com/YosysHQ/yosys/issues/5151
+read_verilog -sv <<EOT
+module expr_postsub_comb (
+    input logic [7:0] in_val_m2,
+    input logic [7:0] sub_val_m2,
+    output logic [7:0] out_diff_m2,
+    output logic [7:0] var_out_m2
+);
+    logic [7:0] var_m2;
+    always_comb begin
+      var_m2 = in_val_m2;
+      out_diff_m2 = (var_m2--) - sub_val_m2;
+      var_out_m2 = var_m2;
+    end
+
+    always_comb assert(out_diff_m2 == in_val_m2 - sub_val_m2);
+endmodule
+EOT
+
+prep
+chformal -lower
+sat -prove-asserts -verify
+
+design -reset
+
+read_verilog -sv <<EOT
+module top(
+	input logic [7:0] a,
+	output logic [7:0] pre_inc,
+	output logic [7:0] pre_dec,
+	output logic [7:0] post_inc,
+	output logic [7:0] post_dec
+);
+
+logic [7:0] a_pre_inc, a_pre_dec, a_post_inc, a_post_dec;
+always_comb begin
+	a_pre_inc = a;
+	a_pre_dec = a;
+	a_post_inc = a;
+	a_post_dec = a;
+
+	pre_inc = ++a_pre_inc;
+	pre_dec = --a_pre_dec;
+	post_inc = a_post_inc++;
+	post_dec = a_post_dec--;
+end
+
+wire [7:0] a_inc = a + 1;
+wire [7:0] a_dec = a - 1;
+
+always_comb begin
+	assert(a_pre_inc == a_inc);
+	assert(a_pre_dec == a_dec);
+	assert(a_post_inc == a_inc);
+	assert(a_post_dec == a_dec);
+
+	assert(pre_inc == a_inc);
+	assert(pre_dec == a_dec);
+	assert(post_inc == a);
+	assert(post_dec == a);
+end
+
+endmodule
+EOT
+
+prep
+chformal -lower
+sat -prove-asserts -verify