diff --git a/Makefile b/Makefile
index 6c9bce554..41b682fbf 100644
--- a/Makefile
+++ b/Makefile
@@ -177,7 +177,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.59+44
+YOSYS_VER := 0.59+62
 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1)
 YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2)
 YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'.' -f3)
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 61dd5e009..d9f14469b 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -116,21 +116,21 @@ void reset_auto_counter_id(RTLIL::IdString id, bool may_rename)
 	if (*it == '$' && may_rename && !norename)
 		auto_name_map[id] = auto_name_counter++;
 
-	if (*it != '\\' || *it != '_' || (it + 1) == it_end)
+	if (*it != '\\' || (it + 1) == it_end || *(it + 1) != '_' || (it + 2) == it_end)
 		return;
 
+	std::string s;
 	it += 2;
-	auto start = it;
 	while (it != it_end) {
 		char ch = *it;
 		if (ch == '_' && (it + 1) == it_end)
-			continue;
+			break;
 		if (ch < '0' || ch > '9')
 			return;
+		s.push_back(ch);
+		++it;
 	}
 
-	std::string s;
-	std::copy(start, it_end, std::back_inserter(s));
 	int num = atoi(s.c_str());
 	if (num >= auto_name_offset)
 		auto_name_offset = num + 1;
diff --git a/kernel/driver.cc b/kernel/driver.cc
index d8b104117..726e25302 100644
--- a/kernel/driver.cc
+++ b/kernel/driver.cc
@@ -158,7 +158,6 @@ extern "C" {
 
 void yosys_atexit()
 {
-	RTLIL::OwningIdString::collect_garbage(false);
 #if defined(YOSYS_ENABLE_READLINE) || defined(YOSYS_ENABLE_EDITLINE)
 	if (!yosys_history_file.empty()) {
 #if defined(YOSYS_ENABLE_READLINE)
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 20cce6029..06643a78b 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -248,15 +248,14 @@ struct IdStringCollector {
 int64_t RTLIL::OwningIdString::gc_ns;
 int RTLIL::OwningIdString::gc_count;
 
-void RTLIL::OwningIdString::collect_garbage(bool trace)
+void RTLIL::OwningIdString::collect_garbage()
 {
 	int64_t start = PerformanceTimer::query();
 #ifndef YOSYS_NO_IDS_REFCNT
 	IdStringCollector collector;
-	if (trace)
-		for (auto &[idx, design] : *RTLIL::Design::get_all_designs()) {
-			collector.trace(*design);
-		}
+	for (auto &[idx, design] : *RTLIL::Design::get_all_designs()) {
+		collector.trace(*design);
+	}
 	int size = GetSize(global_id_storage_);
 	for (int i = static_cast<int>(StaticId::STATIC_ID_END); i < size; ++i) {
 		RTLIL::IdString::Storage &storage = global_id_storage_.at(i);
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 8cf5ddff3..25064057d 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -574,7 +574,7 @@ struct RTLIL::OwningIdString : public RTLIL::IdString {
 	}
 
 	// Collect all non-owning references.
-	static void collect_garbage(bool trace = true);
+	static void collect_garbage();
 	static int64_t garbage_collection_ns() { return gc_ns; }
 	static int garbage_collection_count() { return gc_count; }
 
@@ -1734,6 +1734,8 @@ public:
 	operator std::vector<RTLIL::SigChunk>() const;
 	operator std::vector<RTLIL::SigBit>() const { return to_sigbit_vector(); }
 	const RTLIL::SigBit &at(int offset, const RTLIL::SigBit &defval) { return offset < size() ? (*this)[offset] : defval; }
+	RTLIL::SigBit& at(int offset) { return (*this)[offset]; }
+	RTLIL::SigBit at(int offset) const { return (*this)[offset]; }
 
 	[[nodiscard]] Hasher hash_into(Hasher h) const {
 		Hasher::hash_t val;
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 2e01d72a3..0b6cf70ce 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -263,6 +263,7 @@ void yosys_shutdown()
 
 	delete yosys_design;
 	yosys_design = NULL;
+	RTLIL::OwningIdString::collect_garbage();
 
 	for (auto f : log_files)
 		if (f != stderr)
diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc
index e76d70a1a..22b119800 100644
--- a/techlibs/common/Makefile.inc
+++ b/techlibs/common/Makefile.inc
@@ -28,7 +28,6 @@ $(eval $(call add_share_file,share,techlibs/common/adff2dff.v))
 $(eval $(call add_share_file,share,techlibs/common/dff2ff.v))
 $(eval $(call add_share_file,share,techlibs/common/gate2lut.v))
 $(eval $(call add_share_file,share,techlibs/common/cmp2lut.v))
-$(eval $(call add_share_file,share,techlibs/common/cells.lib))
 $(eval $(call add_share_file,share,techlibs/common/mul2dsp.v))
 $(eval $(call add_share_file,share,techlibs/common/abc9_model.v))
 $(eval $(call add_share_file,share,techlibs/common/abc9_map.v))
diff --git a/techlibs/common/cells.lib b/techlibs/common/cells.lib
deleted file mode 100644
index eb89036d7..000000000
--- a/techlibs/common/cells.lib
+++ /dev/null
@@ -1,108 +0,0 @@
-library(yosys_cells) {
-	cell(DFF_N) {
-		ff(IQ, IQN) {
-			clocked_on: "!C";
-			next_state: "D";
-		}
-		pin(D) { direction: input; }
-		pin(C) { direction: input; clock: true; }
-		pin(Q) { direction: output; function: "IQ"; }
-	}
-	cell(DFF_P) {
-		ff(IQ, IQN) {
-			clocked_on: "C";
-			next_state: "D";
-		}
-		pin(D) { direction: input; }
-		pin(C) { direction: input; clock: true; }
-		pin(Q) { direction: output; function: "IQ"; }
-	}
-	cell(DFF_NN0) {
-		ff(IQ, IQN) {
-			clocked_on: "!C";
-			next_state: "D";
-			clear: "!R";
-		}
-		pin(D) { direction: input; }
-		pin(R) { direction: input; }
-		pin(C) { direction: input; clock: true; }
-		pin(Q) { direction: output; function: "IQ"; }
-	}
-	cell(DFF_NN1) {
-		ff(IQ, IQN) {
-			clocked_on: "!C";
-			next_state: "D";
-			preset: "!R";
-		}
-		pin(D) { direction: input; }
-		pin(R) { direction: input; }
-		pin(C) { direction: input; clock: true; }
-		pin(Q) { direction: output; function: "IQ"; }
-	}
-	cell(DFF_NP0) {
-		ff(IQ, IQN) {
-			clocked_on: "!C";
-			next_state: "D";
-			clear: "R";
-		}
-		pin(D) { direction: input; }
-		pin(R) { direction: input; }
-		pin(C) { direction: input; clock: true; }
-		pin(Q) { direction: output; function: "IQ"; }
-	}
-	cell(DFF_NP1) {
-		ff(IQ, IQN) {
-			clocked_on: "!C";
-			next_state: "D";
-			preset: "R";
-		}
-		pin(D) { direction: input; }
-		pin(R) { direction: input; }
-		pin(C) { direction: input; clock: true; }
-		pin(Q) { direction: output; function: "IQ"; }
-	}
-	cell(DFF_PN0) {
-		ff(IQ, IQN) {
-			clocked_on: "C";
-			next_state: "D";
-			clear: "!R";
-		}
-		pin(D) { direction: input; }
-		pin(R) { direction: input; }
-		pin(C) { direction: input; clock: true; }
-		pin(Q) { direction: output; function: "IQ"; }
-	}
-	cell(DFF_PN1) {
-		ff(IQ, IQN) {
-			clocked_on: "C";
-			next_state: "D";
-			preset: "!R";
-		}
-		pin(D) { direction: input; }
-		pin(R) { direction: input; }
-		pin(C) { direction: input; clock: true; }
-		pin(Q) { direction: output; function: "IQ"; }
-	}
-	cell(DFF_PP0) {
-		ff(IQ, IQN) {
-			clocked_on: "C";
-			next_state: "D";
-			clear: "R";
-		}
-		pin(D) { direction: input; }
-		pin(R) { direction: input; }
-		pin(C) { direction: input; clock: true; }
-		pin(Q) { direction: output; function: "IQ"; }
-	}
-	cell(DFF_PP1) {
-		ff(IQ, IQN) {
-			clocked_on: "C";
-			next_state: "D";
-			preset: "R";
-		}
-		pin(D) { direction: input; }
-		pin(R) { direction: input; }
-		pin(C) { direction: input; clock: true; }
-		pin(Q) { direction: output; function: "IQ"; }
-	}
-}
diff --git a/tests/verilog/.gitignore b/tests/verilog/.gitignore
index d3e8690d5..b16ed0890 100644
--- a/tests/verilog/.gitignore
+++ b/tests/verilog/.gitignore
@@ -1,6 +1,7 @@
 /const_arst.v
 /const_sr.v
 /doubleslash.v
+/reset_auto_counter.v
 /roundtrip_proc_1.v
 /roundtrip_proc_2.v
 /assign_to_reg.v
diff --git a/tests/verilog/reset_auto_counter.ys b/tests/verilog/reset_auto_counter.ys
new file mode 100644
index 000000000..c9756cbac
--- /dev/null
+++ b/tests/verilog/reset_auto_counter.ys
@@ -0,0 +1,17 @@
+read_verilog -sv <<EOT
+module arithmetic (
+    input  logic [7:0] _0_,
+    input  logic [7:0] _1_,
+    output logic [7:0] _2_,
+);
+  assign _2_ = _0_ + _1_;
+
+endmodule : arithmetic
+EOT
+
+hierarchy
+techmap
+write_verilog reset_auto_counter.v
+! ! grep -qE '_0+0_' reset_auto_counter.v
+! ! grep -qE '_0+1_' reset_auto_counter.v
+! ! grep -qE '_0+2_' reset_auto_counter.v