diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc
index b7cbdb36e..d969675a2 100644
--- a/passes/pmgen/Makefile.inc
+++ b/passes/pmgen/Makefile.inc
@@ -6,4 +6,4 @@ passes/pmgen/%_pm.h: passes/pmgen/pmgen.py passes/pmgen/%.pmg
 OBJS += passes/pmgen/test_pmgen.o
 GENFILES += passes/pmgen/test_pmgen_pm.h
 passes/pmgen/test_pmgen.o: passes/pmgen/test_pmgen_pm.h techlibs/ice40/ice40_dsp_pm.h techlibs/xilinx/xilinx_srl_pm.h
-$(eval $(call add_extra_objs,passes/pmgen/test_pmgen_pm.h))
+$(eval $(call add_extra_objs,passes/pmgen/test_pmgen_pm.h))
\ No newline at end of file
diff --git a/passes/silimate/.gitignore b/passes/silimate/.gitignore
index 9342ac23b..dcc658a63 100644
--- a/passes/silimate/.gitignore
+++ b/passes/silimate/.gitignore
@@ -1 +1 @@
-/peepopt*.h
\ No newline at end of file
+/peepopt*.h
diff --git a/tests/peepopt/run-test.sh b/tests/peepopt/run-test.sh
old mode 100755
new mode 100644
diff --git a/tests/various/splitfanout.ys b/tests/silimate/splitfanout.ys
similarity index 100%
rename from tests/various/splitfanout.ys
rename to tests/silimate/splitfanout.ys
diff --git a/tests/various/check.ys b/tests/various/check.ys
index c5b876f0f..0a6afe099 100644
--- a/tests/various/check.ys
+++ b/tests/various/check.ys
@@ -1,6 +1,5 @@
 design -reset
-verific -cfg veri_extract_multiport_rams 1
-read -vlog2k <<EOF
+read_verilog <<EOF
 module top(input clk, input a, input b, output [9:0] x);
 	wire [9:0] ripple;
 	reg [9:0] prev_ripple = 9'b0;
@@ -15,8 +14,7 @@ prep
 check -assert
 
 design -reset
-verific -cfg veri_extract_multiport_rams 1
-read -vlog2k <<EOF
+read_verilog <<EOF
 module top(clk, y, sideread_addr, sideread_data);
 	input wire clk;