diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc
index f61f35e82..9c904e0c7 100644
--- a/frontends/liberty/liberty.cc
+++ b/frontends/liberty/liberty.cc
@@ -313,7 +313,7 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
 		for (auto& [id, var] : {pair{"clear_preset_var1", &clear_preset_var1}, {"clear_preset_var2", &clear_preset_var2}}) {
 			if (child->id == id) {
 				if (child->value.size() != 1)
-					log_error("Unexpected length of clear_preset_var* value %s in LATCH cell %s\n", child->value, name);
+					log_error("Unexpected length of clear_preset_var* value %s in latch cell %s\n", child->value, name);
 				*var = child->value[0];
 			}
 		}
@@ -321,9 +321,9 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
 
 	if (enable_sig.size() == 0 || data_sig.size() == 0) {
 		if (!flag_ignore_miss_data_latch)
-			log_error("LATCH cell %s has no data_in and/or enable attribute.\n", name);
+			log_error("Latch cell %s has no data_in and/or enable attribute.\n", name);
 		else
-			log("Ignored LATCH cell %s with no data_in and/or enable attribute.\n", name);
+			log("Ignored latch cell %s with no data_in and/or enable attribute.\n", name);
 
 		return false;
 	}
@@ -367,7 +367,7 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
 				} else if (*cp_var == 'H') {
 					set_dominates = !neg;
 				} else {
-					log_error("LATCH cell %s has unsupported clear&preset behavior \'%c\'.\n", name, *cp_var);
+					log_error("Latch cell %s has unsupported clear&preset behavior \'%c\'.\n", name, *cp_var);
 				}
 				log_debug("cell %s variable %d cp_var %c set dominates? %d\n", name, (int)neg + 1, *cp_var, set_dominates);
 				// S&R priority is well-defined now
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index 5a597aa5b..9320c6acc 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -261,7 +261,7 @@ struct FfSpec {
 	bool ctrlpol = false; // clock for ff, enable for latch
 	bool has_reset = false, rstpol = false, rstval = false;
 	bool has_sr = false, setpol = false, clrpol = false;
-	bool has_enable = false, enapol = false; // ff clock enable, not used for latch
+	bool dff_has_enable = false, dff_enapol = false;
 };
 
 struct BestCell {
@@ -347,7 +347,7 @@ static void find_cell(std::vector<const LibertyAst *> cells, IdString cell_type,
 {
 	BestCell best;
 
-	log_assert(!(spec.has_sr && spec.enapol) && "set/reset cell with enable is unimplemented due to lack of cells for testing");
+	log_assert(!(spec.has_sr && spec.dff_enapol) && "set/reset cell with enable is unimplemented due to lack of cells for testing");
 
 	// ff stores its state in a "ff" group with a "clocked_on" control pin, latch in a "latch" group with an "enable"
 	const char *group = spec.is_latch ? "latch" : "ff";
@@ -371,7 +371,7 @@ static void find_cell(std::vector<const LibertyAst *> cells, IdString cell_type,
 			if (!parse_pin(cell, storage->find("data_in"), cell_data_pin, cell_data_pol))
 				continue;
 		} else {
-			if (!parse_next_state(cell, storage->find("next_state"), cell_data_pin, cell_data_pol, cell_enable_pin, cell_enable_pol) || (spec.has_enable && (cell_enable_pin.empty() || cell_enable_pol != spec.enapol)))
+			if (!parse_next_state(cell, storage->find("next_state"), cell_data_pin, cell_data_pol, cell_enable_pin, cell_enable_pol) || (spec.dff_has_enable && (cell_enable_pin.empty() || cell_enable_pol != spec.dff_enapol)))
 				continue;
 		}
 
@@ -402,7 +402,7 @@ static void find_cell(std::vector<const LibertyAst *> cells, IdString cell_type,
 			this_cell_ports[cell_clr_pin] = 'R';
 		}
 
-		if (spec.has_enable)
+		if (spec.dff_has_enable)
 			this_cell_ports[cell_enable_pin] = 'E';
 		this_cell_ports[cell_data_pin] = 'D';
 
@@ -601,10 +601,10 @@ struct DfflibmapPass : public Pass {
 		find_cell(merged.cells, ID($_DFF_PP0_), {.ctrlpol=true, .has_reset=true, .rstpol=true}, dont_use_cells);
 		find_cell(merged.cells, ID($_DFF_PP1_), {.ctrlpol=true, .has_reset=true, .rstpol=true, .rstval=true}, dont_use_cells);
 
-		find_cell(merged.cells, ID($_DFFE_NN_), {.has_enable=true}, dont_use_cells);
-		find_cell(merged.cells, ID($_DFFE_NP_), {.has_enable=true, .enapol=true}, dont_use_cells);
-		find_cell(merged.cells, ID($_DFFE_PN_), {.ctrlpol=true, .has_enable=true}, dont_use_cells);
-		find_cell(merged.cells, ID($_DFFE_PP_), {.ctrlpol=true, .has_enable=true, .enapol=true}, dont_use_cells);
+		find_cell(merged.cells, ID($_DFFE_NN_), {.dff_has_enable=true}, dont_use_cells);
+		find_cell(merged.cells, ID($_DFFE_NP_), {.dff_has_enable=true, .dff_enapol=true}, dont_use_cells);
+		find_cell(merged.cells, ID($_DFFE_PN_), {.ctrlpol=true, .dff_has_enable=true}, dont_use_cells);
+		find_cell(merged.cells, ID($_DFFE_PP_), {.ctrlpol=true, .dff_has_enable=true, .dff_enapol=true}, dont_use_cells);
 
 		find_cell(merged.cells, ID($_DFFSR_NNN_), {.has_sr=true}, dont_use_cells);
 		find_cell(merged.cells, ID($_DFFSR_NNP_), {.has_sr=true, .clrpol=true}, dont_use_cells);