diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 0dceaedd6..afcec2fbf 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -998,7 +998,7 @@ struct XAigerWriter : AigerWriter { if (map_file.is_open() && !box_port) { log_assert(cursor.is_top()); // TODO driven_by_opaque_box.insert(bit); - map_file << "pi " << pis.size() - 1 << " " << bit.offset + map_file << "input " << pis.size() - 1 << " " << bit.offset << " " << bit.wire->name.c_str() << "\n"; } } else { @@ -1277,7 +1277,7 @@ struct XAigerWriter : AigerWriter { // don't emit it to the mapping file to aid re-integration, but we // do emit a proper PO. if (map_file.is_open() && !driven_by_opaque_box.count(SigBit(w, i))) { - map_file << "po " << proper_pos_counter << " " << i + map_file << "output " << proper_pos_counter << " " << i << " " << w->name.c_str() << "\n"; } proper_pos_counter++; diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 4e455e494..b3be96c37 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -55,17 +55,6 @@ inline int32_t from_big_endian(int32_t i32) { #define log_debug2(...) ; //#define log_debug2(...) log_debug(__VA_ARGS__) -static int decimal_digits(uint32_t n) { - static uint32_t digit_cutoff[9] = { - 10, 100, 1000, 10000, 100000, - 1000000, 10000000, 100000000, 1000000000 - }; - for (int i = 0; i < 9; ++i) { - if (n < digit_cutoff[i]) return i + 1; - } - return 10; -} - struct ConstEvalAig { RTLIL::Module *module; @@ -607,13 +596,12 @@ void AigerReader::parse_aiger_ascii() unsigned l1, l2, l3; // Parse inputs - int digits = decimal_digits(I); for (unsigned i = 1; i <= I; ++i, ++line_count) { if (!(f >> l1)) log_error("Line %u cannot be interpreted as an input!\n", line_count); log_debug2("%d is an input\n", l1); log_assert(!(l1 & 1)); // Inputs can't be inverted - RTLIL::Wire *wire = module->addWire(stringf("$i%0*d", digits, l1 >> 1)); + RTLIL::Wire *wire = module->addWire(stringf("$i%d", l1 >> 1)); wire->port_input = true; module->connect(createWireIfNotExists(module, l1), wire); inputs.push_back(wire); @@ -629,13 +617,13 @@ void AigerReader::parse_aiger_ascii() clk_wire->port_input = true; clk_wire->port_output = false; } - digits = decimal_digits(L); + for (unsigned i = 0; i < L; ++i, ++line_count) { if (!(f >> l1 >> l2)) log_error("Line %u cannot be interpreted as a latch!\n", line_count); log_debug2("%d %d is a latch\n", l1, l2); log_assert(!(l1 & 1)); - RTLIL::Wire *q_wire = module->addWire(stringf("$l%0*d", digits, l1 >> 1)); + RTLIL::Wire *q_wire = module->addWire(stringf("$l%d", l1 >> 1)); module->connect(createWireIfNotExists(module, l1), q_wire); RTLIL::Wire *d_wire = createWireIfNotExists(module, l2); @@ -667,14 +655,13 @@ void AigerReader::parse_aiger_ascii() } // Parse outputs - digits = decimal_digits(O); for (unsigned i = 0; i < O; ++i, ++line_count) { if (!(f >> l1)) log_error("Line %u cannot be interpreted as an output!\n", line_count); std::getline(f, line); // Ignore up to start of next line log_debug2("%d is an output\n", l1); - RTLIL::Wire *wire = module->addWire(stringf("$o%0*d", digits, i)); + RTLIL::Wire *wire = module->addWire(stringf("$o%d", i)); wire->port_output = true; module->connect(wire, createWireIfNotExists(module, l1)); outputs.push_back(wire); @@ -737,10 +724,9 @@ void AigerReader::parse_aiger_binary() log_error("Binary AIGER input is malformed: maximum variable index M is %u, but number of inputs, latches and AND gates adds up to %u.\n", M, I + L + A); // Parse inputs - int digits = decimal_digits(I); for (unsigned i = 1; i <= I; ++i) { log_debug2("%d is an input\n", i); - RTLIL::Wire *wire = module->addWire(stringf("$i%0*d", digits, i)); + RTLIL::Wire *wire = module->addWire(stringf("$i%d", i)); wire->port_input = true; module->connect(createWireIfNotExists(module, i << 1), wire); inputs.push_back(wire); @@ -756,13 +742,13 @@ void AigerReader::parse_aiger_binary() clk_wire->port_input = true; clk_wire->port_output = false; } - digits = decimal_digits(L); + l1 = (I+1) * 2; for (unsigned i = 0; i < L; ++i, ++line_count, l1 += 2) { if (!(f >> l2)) log_error("Line %u cannot be interpreted as a latch!\n", line_count); log_debug("%d %d is a latch\n", l1, l2); - RTLIL::Wire *q_wire = module->addWire(stringf("$l%0*d", digits, l1 >> 1)); + RTLIL::Wire *q_wire = module->addWire(stringf("$l%d", l1 >> 1)); module->connect(createWireIfNotExists(module, l1), q_wire); RTLIL::Wire *d_wire = createWireIfNotExists(module, l2); @@ -794,14 +780,13 @@ void AigerReader::parse_aiger_binary() } // Parse outputs - digits = decimal_digits(O); for (unsigned i = 0; i < O; ++i, ++line_count) { if (!(f >> l1)) log_error("Line %u cannot be interpreted as an output!\n", line_count); std::getline(f, line); // Ignore up to start of next line log_debug2("%d is an output\n", l1); - RTLIL::Wire *wire = module->addWire(stringf("$o%0*d", digits, i)); + RTLIL::Wire *wire = module->addWire(stringf("$o%d", i)); wire->port_output = true; module->connect(wire, createWireIfNotExists(module, l1)); outputs.push_back(wire); @@ -897,7 +882,7 @@ void AigerReader::post_process() RTLIL::Wire* wire = inputs[variable]; log_assert(wire); log_assert(wire->port_input); - log_debug("Renaming input %s", wire); + log("Renaming input %s", wire); RTLIL::Wire *existing = nullptr; if (index == 0) { @@ -911,7 +896,7 @@ void AigerReader::post_process() wire->port_input = false; module->connect(wire, existing); } - log_debug(" -> %s\n", escaped_s.unescape()); + log(" -> %s\n", escaped_s.unescape()); } else { RTLIL::IdString indexed_name = stringf("%s[%d]", escaped_s, index); @@ -922,7 +907,7 @@ void AigerReader::post_process() module->connect(wire, existing); wire->port_input = false; } - log_debug(" -> %s\n", indexed_name.unescape()); + log(" -> %s\n", indexed_name.unescape()); } if (wideports && !existing) { @@ -942,7 +927,7 @@ void AigerReader::post_process() RTLIL::Wire* wire = outputs[variable + co_count]; log_assert(wire); log_assert(wire->port_output); - log_debug("Renaming output %s", wire); + log("Renaming output %s", wire); RTLIL::Wire *existing; if (index == 0) { @@ -958,7 +943,7 @@ void AigerReader::post_process() module->connect(wire, existing); wire = existing; } - log_debug(" -> %s\n", escaped_s.unescape()); + log(" -> %s\n", escaped_s.unescape()); } else { RTLIL::IdString indexed_name = stringf("%s[%d]", escaped_s, index); @@ -970,7 +955,7 @@ void AigerReader::post_process() existing->port_output = true; module->connect(wire, existing); } - log_debug(" -> %s\n", indexed_name.unescape()); + log(" -> %s\n", indexed_name.unescape()); } if (wideports && !existing) { diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index f7e2b53b5..573261276 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -429,8 +429,8 @@ struct Abc9Pass : public ScriptPass else abc9_exe_cmd += stringf(" -box %s", box_file); run_nocheck(abc9_exe_cmd); - run_nocheck(stringf("read_aiger -xaiger -wideports -module_name %s$abc9 -map %s/input.sym %s/output.aig", mod, tempdir_name, tempdir_name)); - run_nocheck(stringf("abc_ops_reintegrate %s", dff_mode ? "-dff" : "")); + run_nocheck(stringf("read_aiger -xaiger -wideports -module_name %s$abc9 %s/output.aig", mod, tempdir_name)); + run_nocheck(stringf("abc_ops_reintegrate -map %s/input.sym %s", tempdir_name, dff_mode ? "-dff" : "")); } else log("Don't call ABC as there is nothing to map.\n"); diff --git a/passes/techmap/abc_ops_reintegrate.cc b/passes/techmap/abc_ops_reintegrate.cc index 65011f680..329e294e1 100644 --- a/passes/techmap/abc_ops_reintegrate.cc +++ b/passes/techmap/abc_ops_reintegrate.cc @@ -34,7 +34,7 @@ inline std::string remap_name(RTLIL::IdString abc9_name) return stringf("$abc$%d$%s", map_autoidx, abc9_name.c_str()+1); } -void reintegrate(RTLIL::Module *module, bool dff_mode) +void reintegrate(RTLIL::Module *module, bool dff_mode, std::string map_filename) { auto design = module->design; log_assert(design); @@ -52,6 +52,68 @@ void reintegrate(RTLIL::Module *module, bool dff_mode) w->attributes.erase(ID::init); } + dict port_name_map; + dict box_name_map; + + // `write_aiger` will name ports according to their index: 0..N + // `read_aiger` will name ports according to their AIG literal: $o(L)..$o(L+N) + // To reconcile these, we need to find L. + unsigned int input_base = 1; + while (true) { + auto w = mapped_mod->wire(stringf("$i%d", input_base)); + if (w) { + break; + } + input_base++; + } + log("input_base = %u\n", input_base); + + unsigned int output_base = 1; + while (true) { + auto w = mapped_mod->wire(stringf("$o%d", output_base)); + if (w) { + break; + } + output_base++; + } + log("output_base = %u\n", output_base); + + if (!map_filename.empty()) { + std::ifstream mf(map_filename); + std::string type, symbol; + int variable, index; + while (mf >> type >> variable >> index >> symbol) { + RTLIL::IdString escaped_s = RTLIL::escape_id(symbol); + if (type == "input") { + if (index == 0) { + port_name_map.insert({stringf("$i%d", variable + input_base), escaped_s}); + } else { + RTLIL::IdString indexed_name = stringf("%s[%d]", escaped_s, index); + port_name_map.insert({stringf("$i%d", variable + input_base), indexed_name}); + } + } + else if (type == "output") { + if (index == 0) { + port_name_map.insert({stringf("$o%d", variable + output_base), escaped_s}); + } else { + RTLIL::IdString indexed_name = stringf("%s[%d]", escaped_s, index); + port_name_map.insert({stringf("$o%d", variable + output_base), indexed_name}); + } + } + else if (type == "box") { + box_name_map.insert({stringf("$box%d", variable), escaped_s}); + } + else if (type == "pseudopo") { + std::string port; + mf >> port; + log("pseudopo variable=%d index=%d symbol=%s port=%s\n", variable, index, symbol, port); + //port_name_map.insert({stringf("$i%d", variable), escaped_s}); + } + else + log_warning("Symbol type '%s' not recognised.\n", type); + } + } + dict> box_ports; for (auto m : design->modules()) { @@ -222,10 +284,18 @@ void reintegrate(RTLIL::Module *module, bool dff_mode) } } else { - RTLIL::Cell *existing_cell = module->cell(mapped_cell->name); + RTLIL::IdString mapped_cell_name = mapped_cell->name; + auto box_name_entry = box_name_map.find(mapped_cell_name); + if (box_name_entry != box_name_map.end()) { + mapped_cell_name = box_name_entry->second; + } + + RTLIL::Cell *existing_cell = module->cell(mapped_cell_name); if (!existing_cell) log_error("Cannot find existing box cell with name '%s' in original design.\n", mapped_cell); + log("matched mapped box %s\n", mapped_cell_name); + if (existing_cell->type.begins_with("$paramod$__ABC9_DELAY\\DELAY=")) { SigBit I = mapped_cell->getPort(ID(i)); SigBit O = mapped_cell->getPort(ID(o)); @@ -347,10 +417,21 @@ void reintegrate(RTLIL::Module *module, bool dff_mode) // Stitch in mapped_mod's inputs/outputs into module for (auto port : mapped_mod->ports) { + RTLIL::IdString mapped_port_name = port; + auto wire_name_entry = port_name_map.find(mapped_port_name); + if (wire_name_entry != port_name_map.end()) { + mapped_port_name = wire_name_entry->second; + } + RTLIL::Wire *mapped_wire = mapped_mod->wire(port); - RTLIL::Wire *wire = module->wire(port); + RTLIL::Wire *wire = module->wire(mapped_port_name); + if (!wire) { + log_error("no wire in module matches mapped_mod port '%s' with mapped name '%s'\n", port.unescape(), mapped_port_name.unescape()); + } log_assert(wire); + log("matched mapped port %s\n", mapped_port_name); + RTLIL::Wire *remap_wire = module->wire(remap_name(port)); RTLIL::SigSpec signal(wire, remap_wire->start_offset-wire->start_offset, GetSize(remap_wire)); log_assert(GetSize(signal) >= GetSize(remap_wire)); @@ -475,12 +556,20 @@ struct AbcOpsReintegratePass : public Pass { log("by first recovering ABC9 boxes, and then stitching in the remaining\n"); log("primary inputs and outputs.\n"); log("\n"); + log(" -dff\n"); + log(" consider flop cells (those instantiating modules marked with\n"); + log(" (* abc9_flop *)) during -prep_{delays,xaiger,box}.\n"); + log("\n"); + log(" -map \n"); + log(" read file with port and latch symbols\n"); + log("\n"); } void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module).\n"); bool dff_mode = false; + std::string map_filename; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { @@ -489,6 +578,10 @@ struct AbcOpsReintegratePass : public Pass { dff_mode = true; continue; } + if (map_filename.empty() && arg == "-map" && argidx+1 < args.size()) { + map_filename = args[++argidx]; + continue; + } } extra_args(args, argidx, design); @@ -501,7 +594,7 @@ struct AbcOpsReintegratePass : public Pass { if (!design->selected_whole_module(mod)) log_error("Can't handle partially selected module %s!\n", mod); - reintegrate(mod, dff_mode); + reintegrate(mod, dff_mode, map_filename); } } } AbcOpsReintegratePass;