From e138c218cc5afe7770ef67abfa3364c83dc8230b Mon Sep 17 00:00:00 2001 From: Marc Emery Date: Thu, 16 Jul 2026 18:12:29 +0200 Subject: [PATCH] gatemate: fix CC_FIFO_40K sim for non 2^n width usages The fifo address calculation is not correct for the the non power of 2 fifo WIDTHs. When using only power of 2 data, the behavior of the fifo is correct (for example 32 bits in 40 bits mode). When using the full bits, the MSB is incorrect (bit 39:32 for 40 bits mode for example). --- techlibs/gatemate/cells_sim.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/gatemate/cells_sim.v b/techlibs/gatemate/cells_sim.v index e4b79c31b..810150c59 100644 --- a/techlibs/gatemate/cells_sim.v +++ b/techlibs/gatemate/cells_sim.v @@ -1683,8 +1683,8 @@ module CC_FIFO_40K ( end always @(*) begin - fifo_wraddr = {wr_pointer[tp-1:0], {(15-tp){1'b0}}}; - fifo_rdaddr = {rd_pointer[tp-1:0], {(15-tp){1'b0}}}; + fifo_wraddr = wr_pointer[tp-1:0] * B_WIDTH; + fifo_rdaddr = rd_pointer[tp-1:0] * A_WIDTH; rdaddr = {rd_pointer[tp], rd_pointer_int[tp-1:0]}; wraddr = {{(15-tp){1'b0}}, wr_pointer[tp], wr_pointer_int[tp:0]};