diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc
index b09184034..b6eb48a68 100644
--- a/backends/blif/blif.cc
+++ b/backends/blif/blif.cc
@@ -187,7 +187,7 @@ struct BlifDumper
 		return subckt_or_gate(config->gates_mode ? design->module(cell_type) : nullptr);
 	}
 
-	void dump_params(const char *command, dict<IdString, Const> &params)
+	void dump_params(const char *command, dict<LeafIdString, Const> &params)
 	{
 		for (auto &param : params) {
 			f << stringf("%s %s ", command, design->twines.unescaped_str(param.first));
diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc
index 4e9c0bbff..8b4c815c7 100644
--- a/backends/cxxrtl/cxxrtl_backend.cc
+++ b/backends/cxxrtl/cxxrtl_backend.cc
@@ -906,7 +906,7 @@ struct CxxrtlWorker {
 				params += ", ";
 			first = false;
 			params += "/*" + param_name + "=*/";
-			IdString id_param_name = cell->twines().find('\\' + param_name);
+			LeafIdString id_param_name = cell->twines().find('\\' + param_name);
 			if (!cell->hasParam(id_param_name))
 				log_cmd_error("Cell `%s.%s' does not have a parameter `%s', which is required by the templated module `%s'.\n",
 				              cell->module, cell, param_name.c_str(), cell_module);
@@ -2282,7 +2282,7 @@ struct CxxrtlWorker {
 		dec_indent();
 	}
 
-	void dump_serialized_metadata(const dict<RTLIL::IdString, RTLIL::Const> &metadata_map) {
+	void dump_serialized_metadata(const dict<RTLIL::LeafIdString, RTLIL::Const> &metadata_map) {
 		// Creating thousands metadata_map objects using initializer lists in a single function results in one of:
 		// 1. Megabytes of stack usage (with __attribute__((optnone))).
 		// 2. Minutes of compile time (without __attribute__((optnone))).
@@ -2325,7 +2325,7 @@ struct CxxrtlWorker {
 		f << escape_c_string(data);
 	}
 
-	void dump_metadata_map(const dict<RTLIL::IdString, RTLIL::Const> &metadata_map) {
+	void dump_metadata_map(const dict<RTLIL::LeafIdString, RTLIL::Const> &metadata_map) {
 		if (metadata_map.empty()) {
 			f << "metadata_map()";
 		} else {
@@ -2358,7 +2358,7 @@ struct CxxrtlWorker {
 
 	void dump_debug_attrs(const RTLIL::AttrObject *object, bool serialize = true)
 	{
-		dict<RTLIL::IdString, RTLIL::Const> attributes = object->attributes;
+		dict<RTLIL::LeafIdString, RTLIL::Const> attributes = object->attributes;
 		// Inherently necessary to get access to the object, so a waste of space to emit.
 		attributes.erase(ID::hdlname);
 		// Internal Yosys attribute that should be removed but isn't.
diff --git a/backends/jny/jny.cc b/backends/jny/jny.cc
index a45d59d3e..3be6ad77d 100644
--- a/backends/jny/jny.cc
+++ b/backends/jny/jny.cc
@@ -345,7 +345,7 @@ struct JnyWriter
         }
     }
 
-    void write_prams(dict<RTLIL::IdString, RTLIL::Const>& params, uint16_t indent_level = 0) {
+    void write_prams(dict<RTLIL::LeafIdString, RTLIL::Const>& params, uint16_t indent_level = 0) {
         const auto _indent = gen_indent(indent_level);
 
         bool first_param{true};
diff --git a/backends/json/json.cc b/backends/json/json.cc
index 13e72e834..195f0ca8b 100644
--- a/backends/json/json.cc
+++ b/backends/json/json.cc
@@ -130,7 +130,7 @@ struct JsonWriter
 		}
 	}
 
-	void write_parameters(const dict<IdString, Const> &parameters, bool for_module=false)
+	void write_parameters(const dict<LeafIdString, Const> &parameters, bool for_module=false)
 	{
 		bool first = true;
 		for (auto &param : parameters) {
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 93074d1de..760ae0bed 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -416,7 +416,7 @@ void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig)
 	}
 }
 
-void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString, RTLIL::Const> &attributes, std::string term = "\n", bool modattr = false, bool regattr = false, bool as_comment = false)
+void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::LeafIdString, RTLIL::Const> &attributes, std::string term = "\n", bool modattr = false, bool regattr = false, bool as_comment = false)
 {
 	if (noattr)
 		return;
@@ -1042,18 +1042,18 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem)
 	}
 }
 
-IdString signed_param_of(RTLIL::IdString port)
+LeafIdString signed_param_of(RTLIL::IdString port)
 {
 	if (port == ID::A)
 		return ID::A_SIGNED;
 	if (port == ID::B)
 		return ID::B_SIGNED;
-	return IdString();
+	return LeafIdString();
 }
 
 void dump_cell_expr_port(std::ostream &f, RTLIL::Cell *cell, RTLIL::IdString port, bool gen_signed = true)
 {
-	IdString signed_param = gen_signed ? signed_param_of(port) : IdString();
+	LeafIdString signed_param = gen_signed ? signed_param_of(port) : LeafIdString();
 	if (signed_param != IdString::Null && cell->parameters.count(signed_param) > 0 && cell->parameters[signed_param].as_bool()) {
 		f << stringf("$signed(");
 		dump_sigspec(f, cell->getPort(port));
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 81f6ef0e4..5d202b5bd 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -192,7 +192,7 @@ std::string AST::type2str(AstNodeType type)
 }
 
 // check if attribute exists and has non-zero value
-bool AstNode::get_bool_attribute(RTLIL::IdString id)
+bool AstNode::get_bool_attribute(RTLIL::LeafIdString id)
 {
 	if (attributes.count(id) == 0)
 		return false;
@@ -1706,7 +1706,7 @@ void AstModule::expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdStr
 
 // create a new parametric module (when needed) and return the name of the generated module - WITH support for interfaces
 // This method is used to explode the interface when the interface is a port of the module (not instantiated inside)
-RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool /*mayfail*/)
+RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::LeafIdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool /*mayfail*/)
 {
 	std::unique_ptr<AstNode> new_ast = NULL;
 	std::string modname = derive_common(design, parameters, &new_ast);
@@ -1795,7 +1795,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
 }
 
 // create a new parametric module (when needed) and return the name of the generated module - without support for interfaces
-RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool /*mayfail*/)
+RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::LeafIdString, RTLIL::Const> &parameters, bool /*mayfail*/)
 {
 	bool quiet = lib || attributes.count(ID::blackbox) || attributes.count(ID::whitebox);
 
@@ -1843,7 +1843,7 @@ std::string AST::derived_module_name(std::string stripped_name, const std::vecto
 }
 
 // create a new parametric module (when needed) and return the name of the generated module
-std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, std::unique_ptr<AstNode>* new_ast_out, bool quiet)
+std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::LeafIdString, RTLIL::Const> &parameters, std::unique_ptr<AstNode>* new_ast_out, bool quiet)
 {
 	std::string stripped_name = name.str();
 	(*new_ast_out) = nullptr;
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 26ddaba3d..702e6e5ca 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -37,7 +37,7 @@ YOSYS_NAMESPACE_BEGIN
 namespace AST
 {
 	TwinePool &ast_name_pool();
-	inline IdString intern_attr_name(const std::string &name) { return ast_name_pool().add(std::string(name)); }
+	inline LeafIdString intern_attr_name(const std::string &name) { return ast_name_pool().add(std::string(name)); }
 	inline std::string attr_name_str(IdString id) { return ast_name_pool().str(id); }
 
 	// all node types, type2str() must be extended
@@ -187,8 +187,8 @@ namespace AST
 		std::vector<std::unique_ptr<AstNode>> children;
 
 		// The list of attributes assigned to this node. Keys are IdStrings
-		std::map<IdString, std::unique_ptr<AstNode>> attributes;
-		bool get_bool_attribute(IdString id);
+		std::map<LeafIdString, std::unique_ptr<AstNode>> attributes;
+		bool get_bool_attribute(LeafIdString id);
 		bool get_bool_attribute(const std::string &id) { return get_bool_attribute(intern_attr_name(id)); }
 
 		// node content - most of it is unused in most node types
@@ -357,7 +357,7 @@ namespace AST
 		// to evaluate widths of dynamic ranges)
 		std::unique_ptr<AstNode> clone_at_zero();
 
-		void set_attribute(RTLIL::IdString key, std::unique_ptr<AstNode> node)
+		void set_attribute(RTLIL::LeafIdString key, std::unique_ptr<AstNode> node)
 		{
 			node->set_in_param_flag(true);
 			attributes[key] = std::move(node);
@@ -401,9 +401,9 @@ namespace AST
 	struct AstModule : RTLIL::Module {
 		std::unique_ptr<AstNode> ast;
 		bool nolatches, nomeminit, nomem2reg, mem2reg, noblackbox, lib, nowb, noopt, icells, pwires, autowire;
-		RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail) override;
-		RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail) override;
-		std::string derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, std::unique_ptr<AstNode>* new_ast_out, bool quiet = false);
+		RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::LeafIdString, RTLIL::Const> &parameters, bool mayfail) override;
+		RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::LeafIdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail) override;
+		std::string derive_common(RTLIL::Design *design, const dict<RTLIL::LeafIdString, RTLIL::Const> &parameters, std::unique_ptr<AstNode>* new_ast_out, bool quiet = false);
 		void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces) override;
 		bool reprocess_if_necessary(RTLIL::Design *design) override;
 		RTLIL::Module *clone() const override;
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index f98ff82f9..7b7a742bc 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -2121,7 +2121,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 					continue;
 				}
 				if (child->type == AST_PARASET) {
-					IdString paraname = current_module->twines().add(child->str.empty() ? stringf("$%d", ++para_counter) : child->str);
+					LeafIdString paraname = current_module->twines().add(child->str.empty() ? stringf("$%d", ++para_counter) : child->str);
 					const auto* value = child->children[0].get();
 					if (value->type == AST_REALVALUE)
 						log_file_warning(location.to_loc(), "Replacing floating point parameter %s.%s = %f with string.\n",
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 458c92e26..3d0d27fe2 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -749,14 +749,14 @@ const RTLIL::Module* AstNode::lookup_cell_module()
 
 	// build a mapping from true param name to param value
 	size_t para_counter = 0;
-	dict<RTLIL::IdString, RTLIL::Const> cell_params_map;
+	dict<RTLIL::LeafIdString, RTLIL::Const> cell_params_map;
 	for (auto& child : children) {
 		if (child->type != AST_PARASET)
 			continue;
 
 		if (child->str.empty() && para_counter >= module->avail_parameters.size())
 			return nullptr; // let hierarchy handle this error
-		IdString paraname = child->str.empty() ? module->avail_parameters[para_counter++]
+		LeafIdString paraname = child->str.empty() ? module->avail_parameters[para_counter++]
 				: module->twines().add(std::string(child->str));
 
 		const AstNode *value = child->children[0].get();
@@ -767,7 +767,7 @@ const RTLIL::Module* AstNode::lookup_cell_module()
 
 	// put the parameters in order and generate the derived module name
 	std::vector<std::pair<std::string, RTLIL::Const>> named_parameters;
-	for (RTLIL::IdString param : module->avail_parameters) {
+	for (RTLIL::LeafIdString param : module->avail_parameters) {
 		auto it = cell_params_map.find(param);
 		if (it != cell_params_map.end())
 			named_parameters.emplace_back(module->twines().str(it->first), it->second);
@@ -965,7 +965,7 @@ static bool is_autonamed_block(const std::string &str) {
 // nosync to local variables as necessary
 static void check_auto_nosync(AstNode *node)
 {
-	std::vector<RTLIL::IdString> attrs_to_drop;
+	std::vector<RTLIL::LeafIdString> attrs_to_drop;
 	for (const auto& elem : node->attributes) {
 		std::string attr_str = attr_name_str(elem.first);
 		// skip attributes that don't begin with the prefix
@@ -994,7 +994,7 @@ static void check_auto_nosync(AstNode *node)
 	}
 
 	// remove the attributes we've "consumed"
-	for (IdString id : attrs_to_drop) {
+	for (LeafIdString id : attrs_to_drop) {
 		auto it = node->attributes.find(id);
 		node->attributes.erase(it);
 	}
diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc
index 057e94109..9664ce5b3 100644
--- a/frontends/blif/blifparse.cc
+++ b/frontends/blif/blifparse.cc
@@ -130,8 +130,8 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, int a
 		return wire;
 	};
 
-	dict<RTLIL::IdString, RTLIL::Const> *obj_attributes = nullptr;
-	dict<RTLIL::IdString, RTLIL::Const> *obj_parameters = nullptr;
+	dict<RTLIL::LeafIdString, RTLIL::Const> *obj_attributes = nullptr;
+	dict<RTLIL::LeafIdString, RTLIL::Const> *obj_parameters = nullptr;
 
 	dict<RTLIL::IdString, std::pair<int, bool>> wideports_cache;
 
@@ -322,7 +322,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, int a
 			if (!strcmp(cmd, ".attr") || !strcmp(cmd, ".param")) {
 				char *n = strtok(NULL, " \t\r\n");
 				char *v = strtok(NULL, "\r\n");
-				IdString id_n = design->twines.add(RTLIL::escape_id(n));
+				LeafIdString id_n = design->twines.add(RTLIL::escape_id(n));
 				Const const_v;
 				if (v[0] == '"') {
 					std::string str(v+1);
diff --git a/frontends/json/jsonparse.cc b/frontends/json/jsonparse.cc
index cb7c9798e..7d57ad0e2 100644
--- a/frontends/json/jsonparse.cc
+++ b/frontends/json/jsonparse.cc
@@ -274,14 +274,14 @@ Const json_parse_attr_param_value(JsonNode *node)
 	return value;
 }
 
-void json_parse_attr_param(RTLIL::Design *design, dict<IdString, Const> &results, JsonNode *node)
+void json_parse_attr_param(RTLIL::Design *design, dict<LeafIdString, Const> &results, JsonNode *node)
 {
 	if (node->type != 'D')
 		log_error("JSON attributes or parameters node is not a dictionary.\n");
 
 	for (auto it : node->data_dict)
 	{
-		IdString key = design->twines.add(RTLIL::escape_id(it.first.c_str()));
+		LeafIdString key = design->twines.add(RTLIL::escape_id(it.first.c_str()));
 		Const value = json_parse_attr_param_value(it.second);
 		results[key] = value;
 	}
diff --git a/frontends/rpc/rpc_frontend.cc b/frontends/rpc/rpc_frontend.cc
index ca18f7be7..1021ea2f7 100644
--- a/frontends/rpc/rpc_frontend.cc
+++ b/frontends/rpc/rpc_frontend.cc
@@ -115,7 +115,7 @@ struct RpcServer {
 		return modules;
 	}
 
-	std::pair<std::string, std::string> derive_module(const RTLIL::Design *design, const std::string &module, const dict<IdString, RTLIL::Const> &parameters) {
+	std::pair<std::string, std::string> derive_module(const RTLIL::Design *design, const std::string &module, const dict<LeafIdString, RTLIL::Const> &parameters) {
 		Json::object json_parameters;
 		for (auto &param : parameters) {
 			std::string type, value;
@@ -157,7 +157,7 @@ struct RpcServer {
 struct RpcModule : RTLIL::Module {
 	std::shared_ptr<RpcServer> server;
 
-	RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool /*mayfail*/) override {
+	RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::LeafIdString, RTLIL::Const> &parameters, bool /*mayfail*/) override {
 		std::string stripped_name = name.str();
 		if (stripped_name.compare(0, 9, "$abstract") == 0)
 			stripped_name = stripped_name.substr(9);
diff --git a/frontends/rtlil/rtlil_frontend.cc b/frontends/rtlil/rtlil_frontend.cc
index 9970b15ac..8a7339933 100644
--- a/frontends/rtlil/rtlil_frontend.cc
+++ b/frontends/rtlil/rtlil_frontend.cc
@@ -46,7 +46,7 @@ struct RTLILFrontendWorker {
 	std::string_view line;
 
 	RTLIL::Module *current_module;
-	dict<RTLIL::IdString, RTLIL::Const> attrbuf;
+	dict<RTLIL::LeafIdString, RTLIL::Const> attrbuf;
 	std::vector<std::vector<RTLIL::SwitchRule*>*> switch_stack;
 	std::vector<RTLIL::CaseRule*> case_stack;
 
@@ -516,7 +516,7 @@ struct RTLILFrontendWorker {
 
 	void parse_attribute()
 	{
-		IdString id = parse_twine();
+		LeafIdString id = parse_leaf_twine();
 		RTLIL::Const c = parse_const();
 		attrbuf.insert({std::move(id), std::move(c)});
 		expect_eol();
@@ -604,6 +604,16 @@ struct RTLILFrontendWorker {
 		return *t;
 	}
 
+	// Attribute and parameter names are leaves, Yosys never writes them as suffix twines
+	LeafIdString parse_leaf_twine()
+	{
+		IdString ref = parse_twine();
+		if (!design->twines[ref].is_leaf())
+			error("Expected leaf twine for attribute or parameter name, got suffix twine `%s'.",
+					design->twines.str(ref));
+		return design->twines.flatten(ref);
+	}
+
 	void parse_twines()
 	{
 		expect_eol();
@@ -654,7 +664,7 @@ struct RTLILFrontendWorker {
 
 	void parse_parameter()
 	{
-		IdString id = parse_twine();
+		LeafIdString id = parse_leaf_twine();
 		current_module->avail_parameters(id);
 		if (try_parse_eol())
 			return;
@@ -790,7 +800,7 @@ struct RTLILFrontendWorker {
 
 	void legalize_width_parameter(RTLIL::Cell *cell, RTLIL::IdString port_name)
 	{
-		IdString width_param = design->twines.find(design->twines.str(port_name) + "_WIDTH");
+		LeafIdString width_param = design->twines.find(design->twines.str(port_name) + "_WIDTH");
 		if (width_param == IdString::Null || cell->parameters.count(width_param) == 0)
 			return;
 		RTLIL::Const &param = cell->parameters.at(width_param);
@@ -835,7 +845,7 @@ struct RTLILFrontendWorker {
 				} else if (try_parse_keyword("unsized")) {
 					is_unsized = true;
 				}
-				IdString param_name = parse_twine();
+				LeafIdString param_name = parse_leaf_twine();
 				RTLIL::Const val = parse_const();
 				if (is_signed)
 					val.flags |= RTLIL::CONST_FLAG_SIGNED;
diff --git a/frontends/slang/lib b/frontends/slang/lib
index d8a11dbca..8c5fec170 160000
--- a/frontends/slang/lib
+++ b/frontends/slang/lib
@@ -1 +1 @@
-Subproject commit d8a11dbca4493fcb078812747e242aa677bacd45
+Subproject commit 8c5fec17036dae3db818343743c4ee00a29b639d
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index bf96cce0a..0e860dd0d 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -441,7 +441,7 @@ static const std::string verific_unescape(const char *value)
 }
 #endif
 
-void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, DesignObj *obj, Netlist *nl, int wire_width_hint)
+void VerificImporter::import_attributes(dict<RTLIL::LeafIdString, RTLIL::Const> &attributes, DesignObj *obj, Netlist *nl, int wire_width_hint)
 {
 	if (!obj)
 		return;
@@ -1586,7 +1586,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 	const char *param_value ;
 	MapIter mi;
 	FOREACH_PARAMETER_OF_NETLIST(nl, mi, param_name, param_value) {
-		IdString param_id = design->twines.add(RTLIL::escape_id(param_name));
+		LeafIdString param_id = design->twines.add(RTLIL::escape_id(param_name));
 		module->avail_parameters(param_id);
 		const TypeRange *tr = nl->GetTypeRange(param_name) ;
 		const char* type_name = (tr) ? tr->GetTypeName() : nullptr;
diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h
index e489803a2..861115879 100644
--- a/frontends/verific/verific.h
+++ b/frontends/verific/verific.h
@@ -88,7 +88,7 @@ public:
 	RTLIL::SigBit net_map_at(Verific::Net *net);
 
 	RTLIL::IdString new_verific_id(Verific::DesignObj *obj);
-	void import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, Verific::DesignObj *obj, Verific::Netlist  *nl = nullptr, int wire_width_hint = -1);
+	void import_attributes(dict<RTLIL::LeafIdString, RTLIL::Const> &attributes, Verific::DesignObj *obj, Verific::Netlist  *nl = nullptr, int wire_width_hint = -1);
 
 	RTLIL::SigBit netToSigBit(Verific::Net *net);
 	RTLIL::SigSpec operatorInput(Verific::Instance *inst);
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 3bfb7943a..353408a5c 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -550,7 +550,7 @@ struct VerilogFrontend : public Frontend {
 		for (auto &child : parse_state.current_ast->children) {
 			if (child->type == AST::AST_MODULE)
 				for (auto &attr : attributes) {
-					IdString attr_id = AST::intern_attr_name(attr);
+					LeafIdString attr_id = AST::intern_attr_name(attr);
 					if (child->attributes.count(attr_id) == 0)
 						child->attributes[attr_id] = AST::AstNode::mkconst_int(top_loc, 1, false);
 				}
diff --git a/kernel/cellaigs.cc b/kernel/cellaigs.cc
index 91da8286c..c877c3097 100644
--- a/kernel/cellaigs.cc
+++ b/kernel/cellaigs.cc
@@ -94,7 +94,7 @@ struct AigMaker
 	int inport(IdString portname, int portbit = 0, bool inverter = false)
 	{
 		if (portbit >= GetSize(cell->getPort(portname))) {
-			IdString signed_param = cell->twines().find(
+			LeafIdString signed_param = cell->twines().find(
 				cell->twines().str(portname) + "_SIGNED");
 		if (signed_param != IdString::Null && cell->parameters.count(signed_param) && cell->getParam(signed_param).as_bool())
 				return inport(portname, GetSize(cell->getPort(portname))-1, inverter);
diff --git a/kernel/cost.cc b/kernel/cost.cc
index 230afdeb1..05d71a1f9 100644
--- a/kernel/cost.cc
+++ b/kernel/cost.cc
@@ -105,7 +105,7 @@ static bool is_free(RTLIL::IdString type)
 unsigned int max_inp_width(RTLIL::Cell *cell)
 {
 	unsigned int max = 0;
-	RTLIL::IdString input_width_params[] = {
+	RTLIL::LeafIdString input_width_params[] = {
 	  ID::WIDTH,
 	  ID::A_WIDTH,
 	  ID::B_WIDTH,
@@ -115,7 +115,7 @@ unsigned int max_inp_width(RTLIL::Cell *cell)
 	if (cell->type == ID($bmux))
 		return cell->getParam(ID::WIDTH).as_int() << cell->getParam(ID::S_WIDTH).as_int();
 
-	for (RTLIL::IdString param : input_width_params)
+	for (RTLIL::LeafIdString param : input_width_params)
 		if (cell->hasParam(param))
 			max = std::max(max, (unsigned int)cell->getParam(param).as_int());
 	return max;
@@ -124,7 +124,7 @@ unsigned int max_inp_width(RTLIL::Cell *cell)
 unsigned int port_width_sum(RTLIL::Cell *cell)
 {
 	unsigned int sum = 0;
-	RTLIL::IdString port_width_params[] = {
+	RTLIL::LeafIdString port_width_params[] = {
 	  ID::WIDTH, ID::A_WIDTH, ID::B_WIDTH, ID::S_WIDTH, ID::Y_WIDTH,
 	};
 
diff --git a/kernel/ff.h b/kernel/ff.h
index e246a91db..75e73b9b3 100644
--- a/kernel/ff.h
+++ b/kernel/ff.h
@@ -169,7 +169,7 @@ struct FfData : FfTypeData {
 	Const val_init;
 	// The FF data width in bits.
 	int width;
-	dict<IdString, Const> attributes;
+	dict<LeafIdString, Const> attributes;
 
 	FfData(Module *module = nullptr, FfInitVals *initvals = nullptr, IdString name = IdString()) : module(module), initvals(initvals), cell(nullptr), name(name) {
 		width = 0;
diff --git a/kernel/functional.cc b/kernel/functional.cc
index c571fc603..60264e0ab 100644
--- a/kernel/functional.cc
+++ b/kernel/functional.cc
@@ -246,7 +246,7 @@ private:
 		return handle_alu(g, factory.bitwise_or(p, g), g.width(), false, ci, factory.constant(Const(State::S0, 1))).at(ID(CO));
 	}
 public:
-	std::variant<dict<IdString, Node>, Node> handle(IdString cellName, IdString cellType, dict<IdString, Const> parameters, dict<IdString, Node> inputs)
+	std::variant<dict<IdString, Node>, Node> handle(IdString cellName, IdString cellType, dict<LeafIdString, Const> parameters, dict<IdString, Node> inputs)
 	{
 		int a_width = parameters.at(ID(A_WIDTH), Const(-1)).as_int();
 		int b_width = parameters.at(ID(B_WIDTH), Const(-1)).as_int();
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 372cd548e..a8df1885e 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -637,12 +637,12 @@ RTLIL::Const RTLIL::Const::extract(int offset, int len, RTLIL::State padding) co
 }
 #undef check /* check(condition) for Const */
 
-bool RTLIL::AttrObject::has_attribute(RTLIL::IdString id) const
+bool RTLIL::AttrObject::has_attribute(RTLIL::LeafIdString id) const
 {
 	return attributes.count(id);
 }
 
-void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
+void RTLIL::AttrObject::set_bool_attribute(RTLIL::LeafIdString id, bool value)
 {
 	if (value)
 		attributes[id] = RTLIL::Const(1);
@@ -650,7 +650,7 @@ void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
 		attributes.erase(id);
 }
 
-bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
+bool RTLIL::AttrObject::get_bool_attribute(RTLIL::LeafIdString id) const
 {
 	const auto it = attributes.find(id);
 	if (it == attributes.end())
@@ -658,7 +658,7 @@ bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
 	return it->second.as_bool();
 }
 
-void RTLIL::AttrObject::set_string_attribute(RTLIL::IdString id, string value)
+void RTLIL::AttrObject::set_string_attribute(RTLIL::LeafIdString id, string value)
 {
 	if (value.empty())
 		attributes.erase(id);
@@ -666,7 +666,7 @@ void RTLIL::AttrObject::set_string_attribute(RTLIL::IdString id, string value)
 		attributes[id] = value;
 }
 
-string RTLIL::AttrObject::get_string_attribute(RTLIL::IdString id) const
+string RTLIL::AttrObject::get_string_attribute(RTLIL::LeafIdString id) const
 {
 	std::string value;
 	const auto it = attributes.find(id);
@@ -675,7 +675,7 @@ string RTLIL::AttrObject::get_string_attribute(RTLIL::IdString id) const
 	return value;
 }
 
-void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
+void RTLIL::AttrObject::set_strpool_attribute(RTLIL::LeafIdString id, const pool<string> &data)
 {
 	string attrval;
 	for (const auto &s : data) {
@@ -686,7 +686,7 @@ void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<str
 	set_string_attribute(id, attrval);
 }
 
-void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
+void RTLIL::AttrObject::add_strpool_attribute(RTLIL::LeafIdString id, const pool<string> &data)
 {
 	pool<string> union_data = get_strpool_attribute(id);
 	union_data.insert(data.begin(), data.end());
@@ -694,7 +694,7 @@ void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<str
 		set_strpool_attribute(id, union_data);
 }
 
-void RTLIL::Design::absorb_attrs(RTLIL::AttrObject *obj, dict<IdString, RTLIL::Const> &&buf)
+void RTLIL::Design::absorb_attrs(RTLIL::AttrObject *obj, dict<LeafIdString, RTLIL::Const> &&buf)
 {
 	obj->attributes = std::move(buf);
 }
@@ -817,7 +817,7 @@ size_t RTLIL::Design::gc_twines()
 
 
 
-pool<string> RTLIL::AttrObject::get_strpool_attribute(IdString id) const
+pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::LeafIdString id) const
 {
 	pool<string> data;
 	if (attributes.count(id) != 0)
@@ -842,7 +842,7 @@ vector<string> RTLIL::AttrObject::get_hdlname_attribute() const
 	return split_tokens(get_string_attribute(ID::hdlname), " ");
 }
 
-void RTLIL::AttrObject::set_intvec_attribute(RTLIL::IdString id, const vector<int> &data)
+void RTLIL::AttrObject::set_intvec_attribute(RTLIL::LeafIdString id, const vector<int> &data)
 {
 	std::stringstream attrval;
 	for (auto &i : data) {
@@ -853,7 +853,7 @@ void RTLIL::AttrObject::set_intvec_attribute(RTLIL::IdString id, const vector<in
 	attributes[id] = RTLIL::Const(attrval.str());
 }
 
-vector<int> RTLIL::AttrObject::get_intvec_attribute(RTLIL::IdString id) const
+vector<int> RTLIL::AttrObject::get_intvec_attribute(RTLIL::LeafIdString id) const
 {
 	vector<int> data;
 	auto it = attributes.find(id);
@@ -1425,7 +1425,7 @@ bool RTLIL::Module::reprocess_if_necessary(RTLIL::Design *)
 	return false;
 }
 
-RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, bool mayfail)
+RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::LeafIdString, RTLIL::Const> &, bool mayfail)
 {
 	if (mayfail)
 		return IdString::Null;
@@ -1433,7 +1433,7 @@ RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString
 }
 
 
-RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, const dict<RTLIL::IdString, RTLIL::Module*> &, const dict<RTLIL::IdString, RTLIL::IdString> &, bool mayfail)
+RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::LeafIdString, RTLIL::Const> &, const dict<RTLIL::IdString, RTLIL::Module*> &, const dict<RTLIL::IdString, RTLIL::IdString> &, bool mayfail)
 {
 	if (mayfail)
 		return IdString::Null;
@@ -1466,7 +1466,7 @@ namespace {
 	{
 		const RTLIL::Module *module;
 		RTLIL::Cell *cell;
-		pool<IdString> expected_params;
+		pool<LeafIdString> expected_params;
 		pool<IdString> expected_ports;
 
 		InternalCellChecker(const RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
@@ -1483,7 +1483,7 @@ namespace {
 					cell_name, cell->type.str(), __FILE__, linenr, buf.str());
 		}
 
-		int param(RTLIL::IdString name)
+		int param(RTLIL::LeafIdString name)
 		{
 			auto it = cell->parameters.find(name);
 			if (it == cell->parameters.end())
@@ -1492,7 +1492,7 @@ namespace {
 			return it->second.as_int();
 		}
 
-		int param_bool(RTLIL::IdString name)
+		int param_bool(RTLIL::LeafIdString name)
 		{
 			int v = param(name);
 			if (GetSize(cell->parameters.at(name)) > 32)
@@ -1502,7 +1502,7 @@ namespace {
 			return v;
 		}
 
-		int param_bool(RTLIL::IdString name, bool expected)
+		int param_bool(RTLIL::LeafIdString name, bool expected)
 		{
 			int v = param_bool(name);
 			if (v != expected)
@@ -1510,14 +1510,14 @@ namespace {
 			return v;
 		}
 
-		void param_bits(RTLIL::IdString name, int width)
+		void param_bits(RTLIL::LeafIdString name, int width)
 		{
 			param(name);
 			if (GetSize(cell->parameters.at(name)) != width)
 				error(__LINE__);
 		}
 
-		std::string param_string(RTLIL::IdString name)
+		std::string param_string(RTLIL::LeafIdString name)
 		{
 			param(name);
 			return cell->parameters.at(name).decode_string();
@@ -2450,12 +2450,10 @@ void RTLIL::Module::sort()
 }
 
 #ifndef NDEBUG
-static void check_id_keys(const RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &keyed)
+static void check_id_keys(const dict<RTLIL::LeafIdString, RTLIL::Const> &keyed)
 {
-	for (auto &it : keyed) {
+	for (auto &it : keyed)
 		log_assert(!it.first.empty());
-		log_assert(design->twines[it.first].is_leaf());
-	}
 }
 #endif
 
@@ -2471,7 +2469,7 @@ void check_module(RTLIL::Module *module, ParallelDispatchThreadPool &thread_pool
 		log_assert(it.first != IdString::Null);
 		log_assert(it.second->width >= 0);
 		log_assert(it.second->size >= 0);
-		check_id_keys(module->design, it.second->attributes);
+		check_id_keys(it.second->attributes);
 		memory_strings.insert(it.second->name.str());
 	}
 
@@ -2488,8 +2486,8 @@ void check_module(RTLIL::Module *module, ParallelDispatchThreadPool &thread_pool
 				log_assert(it2.first != IdString::Null);
 				it2.second.check(const_module);
 			}
-			check_id_keys(const_module->design, it.second->attributes);
-			check_id_keys(const_module->design, it.second->parameters);
+			check_id_keys(it.second->attributes);
+			check_id_keys(it.second->parameters);
 			InternalCellChecker checker(const_module, it.second);
 			checker.check();
 			if (it.second->has_memid()) {
@@ -2522,7 +2520,7 @@ void check_module(RTLIL::Module *module, ParallelDispatchThreadPool &thread_pool
 			log_assert(it.first != IdString::Null);
 			log_assert(it.second->width >= 0);
 			log_assert(it.second->port_id >= 0);
-			check_id_keys(const_module->design, it.second->attributes);
+			check_id_keys(it.second->attributes);
 			if (it.second->port_id) {
 				log_assert(GetSize(const_module->ports) >= it.second->port_id);
 				log_assert(const_module->ports.at(it.second->port_id-1) == it.second->name);
@@ -2580,7 +2578,7 @@ void check_module(RTLIL::Module *module, ParallelDispatchThreadPool &thread_pool
 		it.second.check(module);
 	}
 
-	check_id_keys(module->design, module->attributes);
+	check_id_keys(module->attributes);
 #endif
 }
 
@@ -2603,7 +2601,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
 	TwinePool &dst_twines = new_mod->twines();
 
 	new_mod->avail_parameters.clear();
-	for (IdString param : avail_parameters)
+	for (LeafIdString param : avail_parameters)
 		new_mod->avail_parameters(dst_twines.copy_from(design->twines, param));
 	new_mod->parameter_default_values.clear();
 	for (auto &it : parameter_default_values)
@@ -3061,8 +3059,8 @@ void RTLIL::Module::fixup_ports()
 	}
 }
 
-void RTLIL::copy_attr_dict(dict<IdString, RTLIL::Const> &dst,
-		const dict<IdString, RTLIL::Const> &src,
+void RTLIL::copy_attr_dict(dict<LeafIdString, RTLIL::Const> &dst,
+		const dict<LeafIdString, RTLIL::Const> &src,
 		const RTLIL::Design *src_design, RTLIL::Design *dst_design)
 {
 	if (!src_design || !dst_design || src_design == dst_design) {
@@ -4366,22 +4364,22 @@ RTLIL::PortDir RTLIL::Cell::port_dir(RTLIL::IdString portname) const
 	return PortDir::PD_UNKNOWN;
 }
 
-bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
+bool RTLIL::Cell::hasParam(RTLIL::LeafIdString paramname) const
 {
 	return parameters.count(paramname) != 0;
 }
 
-void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
+void RTLIL::Cell::unsetParam(RTLIL::LeafIdString paramname)
 {
 	parameters.erase(paramname);
 }
 
-void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
+void RTLIL::Cell::setParam(RTLIL::LeafIdString paramname, RTLIL::Const value)
 {
 	parameters[paramname] = std::move(value);
 }
 
-const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
+const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::LeafIdString paramname) const
 {
 	const auto &it = parameters.find(paramname);
 	if (it != parameters.end())
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 4d1c612c9..42ffde295 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -125,10 +125,11 @@ struct SigMap;
 
 namespace RTLIL { using YOSYS_NAMESPACE_PREFIX ID; }
 namespace RTLIL { using YOSYS_NAMESPACE_PREFIX IdString; }
+namespace RTLIL { using YOSYS_NAMESPACE_PREFIX LeafIdString; }
 
 namespace RTLIL {
-	void copy_attr_dict(dict<IdString, RTLIL::Const> &dst,
-			const dict<IdString, RTLIL::Const> &src,
+	void copy_attr_dict(dict<LeafIdString, RTLIL::Const> &dst,
+			const dict<LeafIdString, RTLIL::Const> &src,
 			const RTLIL::Design *src_design, RTLIL::Design *dst_design);
 
 	extern dict<std::string, std::string> constpad;
@@ -636,24 +637,24 @@ public:
 
 struct RTLIL::AttrObject
 {
-	dict<RTLIL::IdString, RTLIL::Const> attributes;
+	dict<RTLIL::LeafIdString, RTLIL::Const> attributes;
 
-	bool has_attribute(RTLIL::IdString id) const;
+	bool has_attribute(RTLIL::LeafIdString id) const;
 
-	void set_bool_attribute(RTLIL::IdString id, bool value=true);
-	bool get_bool_attribute(RTLIL::IdString id) const;
+	void set_bool_attribute(RTLIL::LeafIdString id, bool value=true);
+	bool get_bool_attribute(RTLIL::LeafIdString id) const;
 
 	[[deprecated("Use Module::get_blackbox_attribute() instead.")]]
 	bool get_blackbox_attribute(bool ignore_wb=false) const {
 		return get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));
 	}
 
-	void set_string_attribute(IdString id, string value);
-	string get_string_attribute(RTLIL::IdString id) const;
+	void set_string_attribute(RTLIL::LeafIdString id, string value);
+	string get_string_attribute(RTLIL::LeafIdString id) const;
 
-	void set_strpool_attribute(RTLIL::IdString id, const pool<string> &data);
-	void add_strpool_attribute(RTLIL::IdString id, const pool<string> &data);
-	pool<string> get_strpool_attribute(RTLIL::IdString id) const;
+	void set_strpool_attribute(RTLIL::LeafIdString id, const pool<string> &data);
+	void add_strpool_attribute(RTLIL::LeafIdString id, const pool<string> &data);
+	pool<string> get_strpool_attribute(RTLIL::LeafIdString id) const;
 
 	void set_src_attribute(const std::string &src) {
 		set_string_attribute(ID::src, src);
@@ -665,8 +666,8 @@ struct RTLIL::AttrObject
 	void set_hdlname_attribute(const vector<string> &hierarchy);
 	vector<string> get_hdlname_attribute() const;
 
-	void set_intvec_attribute(IdString id, const vector<int> &data);
-	vector<int> get_intvec_attribute(RTLIL::IdString id) const;
+	void set_intvec_attribute(RTLIL::LeafIdString id, const vector<int> &data);
+	vector<int> get_intvec_attribute(RTLIL::LeafIdString id) const;
 };
 
 struct RTLIL::NamedObject : public RTLIL::AttrObject
@@ -1314,7 +1315,7 @@ struct RTLIL::Design
 		return twines.str(obj->name_);
 	}
 
-	void absorb_attrs(RTLIL::AttrObject *obj, dict<IdString, RTLIL::Const> &&buf);
+	void absorb_attrs(RTLIL::AttrObject *obj, dict<LeafIdString, RTLIL::Const> &&buf);
 
 	size_t gc_twines();
 
@@ -1503,15 +1504,15 @@ public:
 
 	std::vector<RTLIL::SigSig>   connections_;
 
-	idict<RTLIL::IdString> avail_parameters;
-	dict<RTLIL::IdString, RTLIL::Const> parameter_default_values;
+	idict<RTLIL::LeafIdString> avail_parameters;
+	dict<RTLIL::LeafIdString, RTLIL::Const> parameter_default_values;
 	dict<RTLIL::IdString, RTLIL::Memory*> memories;
 	dict<RTLIL::IdString, RTLIL::Process*> processes;
 
 	Module();
 	virtual ~Module();
-	virtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail = false);
-	virtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail = false);
+	virtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::LeafIdString, RTLIL::Const> &parameters, bool mayfail = false);
+	virtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::LeafIdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail = false);
 	virtual size_t count_id(RTLIL::IdString id);
 	virtual void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces);
 	virtual bool reprocess_if_necessary(RTLIL::Design *design);
@@ -2021,7 +2022,7 @@ public:
 	IdString type_impl;
 	YS_NO_UNIQUE_ADDRESS RTLIL::CellTypeMasq type;
 	dict<RTLIL::IdString, RTLIL::SigSpec> connections_;
-	dict<RTLIL::IdString, RTLIL::Const> parameters;
+	dict<RTLIL::LeafIdString, RTLIL::Const> parameters;
 
 	// access cell ports
 	bool hasPort(RTLIL::IdString portname) const;
@@ -2037,10 +2038,10 @@ public:
 	bool output(RTLIL::IdString portname) const;
 	PortDir port_dir(RTLIL::IdString portname) const;
 
-	bool hasParam(RTLIL::IdString paramname) const;
-	void unsetParam(RTLIL::IdString paramname);
-	void setParam(RTLIL::IdString paramname, RTLIL::Const value);
-	const RTLIL::Const &getParam(RTLIL::IdString paramname) const;
+	bool hasParam(RTLIL::LeafIdString paramname) const;
+	void unsetParam(RTLIL::LeafIdString paramname);
+	void setParam(RTLIL::LeafIdString paramname, RTLIL::Const value);
+	const RTLIL::Const &getParam(RTLIL::LeafIdString paramname) const;
 
 	template<typename N, YS_NAME_STRING(N)> bool hasParam(N name) const
 		{ return hasParam(module->twines().add(std::move(name))); }
diff --git a/kernel/scopeinfo.cc b/kernel/scopeinfo.cc
index 6efb88d86..4f59d2c6f 100644
--- a/kernel/scopeinfo.cc
+++ b/kernel/scopeinfo.cc
@@ -101,7 +101,7 @@ bool scopeinfo_has_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs,
 {
 	log_assert(scopeinfo->type == ID($scopeinfo));
 	TwinePool &twines = scopeinfo->twines();
-	IdString key = twines.find(attr_prefix(attrs) + twines.unescaped_str(id));
+	LeafIdString key = twines.find(attr_prefix(attrs) + twines.unescaped_str(id));
 	return key != IdString::Null && scopeinfo->has_attribute(key);
 }
 
@@ -109,7 +109,7 @@ RTLIL::Const scopeinfo_get_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttr
 {
 	log_assert(scopeinfo->type == ID($scopeinfo));
 	TwinePool &twines = scopeinfo->twines();
-	IdString key = twines.find(attr_prefix(attrs) + twines.unescaped_str(id));
+	LeafIdString key = twines.find(attr_prefix(attrs) + twines.unescaped_str(id));
 	if (key == IdString::Null)
 		return RTLIL::Const();
 	auto found = scopeinfo->attributes.find(key);
@@ -118,9 +118,9 @@ RTLIL::Const scopeinfo_get_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttr
 	return found->second;
 }
 
-dict<RTLIL::IdString, RTLIL::Const> scopeinfo_attributes(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs)
+dict<RTLIL::LeafIdString, RTLIL::Const> scopeinfo_attributes(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs)
 {
-	dict<RTLIL::IdString, RTLIL::Const> attributes;
+	dict<RTLIL::LeafIdString, RTLIL::Const> attributes;
 
 	const char *prefix = attr_prefix(attrs);
 	size_t prefix_len = strlen(prefix);
diff --git a/kernel/scopeinfo.h b/kernel/scopeinfo.h
index 34172fbc6..b3395d9ae 100644
--- a/kernel/scopeinfo.h
+++ b/kernel/scopeinfo.h
@@ -444,7 +444,7 @@ bool scopeinfo_has_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs,
 RTLIL::Const scopeinfo_get_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, RTLIL::IdString id);
 
 // Get all attribute from the flattened module or flattened cell corresponding to a $scopeinfo cell.
-dict<RTLIL::IdString, RTLIL::Const> scopeinfo_attributes(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs);
+dict<RTLIL::LeafIdString, RTLIL::Const> scopeinfo_attributes(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs);
 
 YOSYS_NAMESPACE_END
 
diff --git a/kernel/tclapi.cc b/kernel/tclapi.cc
index 21caae041..d45298b98 100644
--- a/kernel/tclapi.cc
+++ b/kernel/tclapi.cc
@@ -279,7 +279,7 @@ static int tcl_get_attr(ClientData, Tcl_Interp *interp, int argc, const char *ar
 	if (!obj)
 		ERROR("object not found")
 
-	IdString attr_twine = search.find(attr_id);
+	LeafIdString attr_twine = yosys_design->twines.find(attr_id);
 
 	if (string_flag) {
 		Tcl_SetObjResult(interp, Tcl_NewStringObj(obj->get_string_attribute(attr_twine).c_str(), -1));
@@ -347,7 +347,7 @@ static int tcl_has_attr(ClientData, Tcl_Interp *interp, int argc, const char *ar
 	if (!obj)
 		ERROR("object not found")
 
-	Tcl_SetObjResult(interp, Tcl_NewStringObj(std::to_string(obj->has_attribute(search.find(attr_id))).c_str(), -1));
+	Tcl_SetObjResult(interp, Tcl_NewStringObj(std::to_string(obj->has_attribute(yosys_design->twines.find(attr_id))).c_str(), -1));
 	return TCL_OK;
 }
 
@@ -403,7 +403,7 @@ static int tcl_set_attr(ClientData, Tcl_Interp *interp, int objc, Tcl_Obj *const
 	if (!obj)
 		ERROR("object not found")
 
-	IdString attr_twine = yosys_design->twines.add(std::string(attr_id));
+	LeafIdString attr_twine = yosys_design->twines.add(std::string(attr_id));
 
 	if (string_flag) {
 		obj->set_string_attribute(attr_twine, Tcl_GetString(objv[i++]));
@@ -473,7 +473,7 @@ static int tcl_get_param(ClientData, Tcl_Interp *interp, int argc, const char *a
 	if (!cell)
 		ERROR("object not found")
 
-	IdString param_twine = search.find(param_id);
+	LeafIdString param_twine = yosys_design->twines.find(param_id);
 	if (!cell->hasParam(param_twine))
 		ERROR("parameter missing")
 
@@ -523,7 +523,7 @@ static int tcl_set_param(ClientData, Tcl_Interp *interp, int objc, Tcl_Obj *cons
 	if (!cell)
 		ERROR("object not found")
 
-	IdString param_twine = yosys_design->twines.add(std::string(param_id));
+	LeafIdString param_twine = yosys_design->twines.add(std::string(param_id));
 
 	if (string_flag) {
 		cell->setParam(param_twine, Const(std::string(Tcl_GetString(objv[i++]))));
diff --git a/passes/cmds/box_derive.cc b/passes/cmds/box_derive.cc
index 024e4101a..115344f78 100644
--- a/passes/cmds/box_derive.cc
+++ b/passes/cmds/box_derive.cc
@@ -75,7 +75,7 @@ struct BoxDerivePass : Pass {
 		}
 		extra_args(args, argidx, d);
 
-		IdString naming_attr_ref = naming_attr.empty() ? IdString::Null : d->twines.find(naming_attr);
+		LeafIdString naming_attr_ref = naming_attr.empty() ? IdString::Null : d->twines.find(naming_attr);
 
 		Module *base_override = nullptr;
 		if (!base_name.empty()) {
@@ -85,7 +85,7 @@ struct BoxDerivePass : Pass {
 				log_cmd_error("Base module %s not found.\n", RTLIL::unescape_id(base_name));
 		}
 
-		dict<std::pair<RTLIL::IdString, dict<RTLIL::IdString, RTLIL::Const>>, Module*> done;
+		dict<std::pair<RTLIL::IdString, dict<RTLIL::LeafIdString, RTLIL::Const>>, Module*> done;
 
 		for (auto module : d->selected_modules()) {
 			for (auto cell : module->selected_cells()) {
diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc
index 84fff9a17..36d6857a2 100644
--- a/passes/cmds/connwrappers.cc
+++ b/passes/cmds/connwrappers.cc
@@ -84,11 +84,11 @@ struct ConnwrappersWorker
 
 				portdecl_t &decl = decls.at(key);
 
-				IdString widthparam = module->twines().find(decl.widthparam);
+				LeafIdString widthparam = module->twines().find(decl.widthparam);
 				if (widthparam == IdString::Null || !cell->parameters.count(widthparam))
 					continue;
 
-				IdString signparam = decl.signparam.empty() ? IdString::Null : module->twines().find(decl.signparam);
+				LeafIdString signparam = decl.signparam.empty() ? IdString::Null : module->twines().find(decl.signparam);
 				if (!decl.signparam.empty() && (signparam == IdString::Null || !cell->parameters.count(signparam)))
 					continue;
 
diff --git a/passes/cmds/design_equal.cc b/passes/cmds/design_equal.cc
index 4b43d7f92..d95f88044 100644
--- a/passes/cmds/design_equal.cc
+++ b/passes/cmds/design_equal.cc
@@ -36,6 +36,8 @@ public:
 
 	IdString a_to_b(IdString ref) const { return search_b.find(pool_a->str(ref)); }
 	IdString b_to_a(IdString ref) const { return search_a.find(pool_b->str(ref)); }
+	LeafIdString a_to_b(LeafIdString ref) const { return pool_b->find_from(*pool_a, ref); }
+	LeafIdString b_to_a(LeafIdString ref) const { return pool_a->find_from(*pool_b, ref); }
 
 	bool same(IdString a, IdString b) const { return pool_a->str(a) == pool_b->str(b); }
 };
@@ -87,7 +89,7 @@ public:
 	std::string compare_attributes(const RTLIL::AttrObject *a, const RTLIL::AttrObject *b)
 	{
 		for (const auto &it : a->attributes) {
-			IdString in_b = bridge.a_to_b(it.first);
+			LeafIdString in_b = bridge.a_to_b(it.first);
 			if (b->attributes.count(in_b) == 0)
 				return "missing attribute " + std::string(mod_a->twines().unescaped_str(it.first)) + " in second design";
 			if (it.second != b->attributes.at(in_b))
@@ -162,7 +164,7 @@ public:
 			return mismatch;
 
 		for (const auto &it : a->parameters) {
-			IdString in_b = bridge.a_to_b(it.first);
+			LeafIdString in_b = bridge.a_to_b(it.first);
 			if (b->parameters.count(in_b) == 0)
 				return "parameter mismatch: missing parameter " + std::string(mod_a->twines().unescaped_str(it.first)) + " in second design";
 			if (it.second != b->parameters.at(in_b))
diff --git a/passes/cmds/example_dt.cc b/passes/cmds/example_dt.cc
index fad2313dd..9ab405592 100644
--- a/passes/cmds/example_dt.cc
+++ b/passes/cmds/example_dt.cc
@@ -175,7 +175,7 @@ struct ExampleDtPass : public Pass
 					} else if (chunk.is_marker()) {
 						Cell *cell = cells[chunk.marker().marker];
 
-						node.set_function(ExampleFn(cell->type, cell->parameters));
+						node.set_function(ExampleFn(cell->type, dict<IdString, Const>(cell->parameters.begin(), cell->parameters.end())));
 						for (auto const &conn : cell->connections()) {
 							if (!dm.celltypes.cell_input(cell->type, conn.first))
 								continue;
diff --git a/passes/cmds/glift.cc b/passes/cmds/glift.cc
index 6fc88f4b3..a0f34aab4 100644
--- a/passes/cmds/glift.cc
+++ b/passes/cmds/glift.cc
@@ -35,7 +35,7 @@ private:
 	RTLIL::Module *module = nullptr;
 
 	const IdString cost_model_wire_name = ID::__glift_weight;
-	const IdString glift_attribute_name = ID::glift;
+	const LeafIdString glift_attribute_name = ID::glift;
 
 
 	RTLIL::SigSpec get_corresponding_taint_signal(RTLIL::SigSpec sig) {
diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc
index c3070c905..37e4a8ca9 100644
--- a/passes/cmds/scc.cc
+++ b/passes/cmds/scc.cc
@@ -356,7 +356,7 @@ struct SccPass : public Pass {
 				{
 					for (auto attr : setAttr)
 					{
-						IdString attr_name = design->twines.add(RTLIL::escape_id(attr.first));
+						LeafIdString attr_name = design->twines.add(RTLIL::escape_id(attr.first));
 						string attr_valstr = attr.second;
 						string index = stringf("%d", scc_counter);
 
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index ecd560279..da0353b7e 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -105,7 +105,7 @@ static bool match_attr_val(const RTLIL::Const &value, const std::string &pattern
 	log_abort();
 }
 
-static bool match_attr(const TwinePool &pool, const dict<IdString, RTLIL::Const> &attributes, const std::string &name_pat, const std::string &value_pat, char match_op)
+static bool match_attr(const TwinePool &pool, const dict<LeafIdString, RTLIL::Const> &attributes, const std::string &name_pat, const std::string &value_pat, char match_op)
 {
 	if (name_pat.find('*') != std::string::npos || name_pat.find('?') != std::string::npos || name_pat.find('[') != std::string::npos) {
 		for (auto &it : attributes) {
@@ -117,18 +117,18 @@ static bool match_attr(const TwinePool &pool, const dict<IdString, RTLIL::Const>
 		}
 	} else {
 		if (name_pat.size() > 0 && (name_pat[0] == '\\' || name_pat[0] == '$')) {
-			IdString key = pool.find(name_pat);
+			LeafIdString key = pool.find(name_pat);
 			if (key != IdString::Null && attributes.count(key) && match_attr_val(attributes.at(key), value_pat, match_op))
 				return true;
 		}
-		IdString key = pool.find("\\" + name_pat);
+		LeafIdString key = pool.find("\\" + name_pat);
 		if (key != IdString::Null && attributes.count(key) && match_attr_val(attributes.at(key), value_pat, match_op))
 			return true;
 	}
 	return false;
 }
 
-static bool match_attr(const TwinePool &pool, const dict<IdString, RTLIL::Const> &attributes, const std::string &match_expr)
+static bool match_attr(const TwinePool &pool, const dict<LeafIdString, RTLIL::Const> &attributes, const std::string &match_expr)
 {
 	size_t pos = match_expr.find_first_of("<!=>");
 
diff --git a/passes/cmds/setattr.cc b/passes/cmds/setattr.cc
index 4f1a19348..f760e5e71 100644
--- a/passes/cmds/setattr.cc
+++ b/passes/cmds/setattr.cc
@@ -46,11 +46,11 @@ struct setunset_t
 	}
 };
 
-static void do_setunset(RTLIL::Design *design, dict<IdString, RTLIL::Const> &attrs, const std::vector<setunset_t> &list)
+static void do_setunset(RTLIL::Design *design, dict<LeafIdString, RTLIL::Const> &attrs, const std::vector<setunset_t> &list)
 {
 	for (auto &item : list)
 		if (item.unset) {
-			IdString name = design->twines.find(item.name);
+			LeafIdString name = design->twines.find(item.name);
 			if (name != IdString::Null)
 				attrs.erase(name);
 		} else
@@ -216,7 +216,7 @@ struct ChparamPass : public Pass {
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		std::vector<setunset_t> setunset_list;
-		dict<RTLIL::IdString, RTLIL::Const> new_parameters;
+		dict<RTLIL::LeafIdString, RTLIL::Const> new_parameters;
 		bool list_mode = false;
 
 		size_t argidx;
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index 802ba5fbe..711f8b214 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -74,7 +74,7 @@ struct ShowWorker
 	const std::vector<std::pair<std::string, RTLIL::Selection>> &label_selections;
 
 	std::map<RTLIL::Const, int> colorattr_cache;
-	RTLIL::IdString colorattr;
+	RTLIL::LeafIdString colorattr;
 
 
 	static uint32_t xorshift32(uint32_t x) {
@@ -486,7 +486,7 @@ struct ShowWorker
 
 			for (auto &p : in_ports) {
 				std::string p_str = design->twines.str(p);
-				IdString signed_param = design->twines.find(p_str + "_SIGNED");
+				LeafIdString signed_param = design->twines.find(p_str + "_SIGNED");
 				bool signed_suffix = genSignedLabels && signed_param != IdString::Null
 									 && cell->hasParam(signed_param)
 									 && cell->getParam(signed_param).as_bool();
@@ -629,7 +629,7 @@ struct ShowWorker
 	ShowWorker(FILE *f, RTLIL::Design *design, std::vector<RTLIL::Design*> &libs, uint32_t colorSeed, bool genWidthLabels,
 			const std::string wireshape, bool genSignedLabels, bool stretchIO, bool enumerateIds, bool abbreviateIds, bool notitle, bool href,
 			const std::vector<std::pair<std::string, RTLIL::Selection>> &color_selections,
-			const std::vector<std::pair<std::string, RTLIL::Selection>> &label_selections, RTLIL::IdString colorattr) :
+			const std::vector<std::pair<std::string, RTLIL::Selection>> &label_selections, RTLIL::LeafIdString colorattr) :
 			f(f), design(design), search(&design->twines), currentColor(colorSeed), genWidthLabels(genWidthLabels), wireshape(wireshape),
 			genSignedLabels(genSignedLabels), stretchIO(stretchIO), enumerateIds(enumerateIds), abbreviateIds(abbreviateIds),
 			notitle(notitle), href(href), color_selections(color_selections), label_selections(label_selections), colorattr(colorattr)
@@ -798,7 +798,7 @@ struct ShowPass : public Pass {
 		bool flag_href = false;
 		bool custom_prefix = false;
 		std::string background = "&";
-		RTLIL::IdString colorattr;
+		RTLIL::LeafIdString colorattr;
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
diff --git a/passes/cmds/splitcells.cc b/passes/cmds/splitcells.cc
index 1e5b302df..c618e2828 100644
--- a/passes/cmds/splitcells.cc
+++ b/passes/cmds/splitcells.cc
@@ -178,7 +178,7 @@ struct SplitcellsWorker
 					}
 				}
 
-				for (IdString paramname : splitparams) {
+				for (LeafIdString paramname : splitparams) {
 					if (slice->hasParam(paramname)) {
 						Const val = slice->getParam(paramname);
 						val = val.extract(slice_lsb, slice_msb-slice_lsb+1);
diff --git a/passes/cmds/timeest.cc b/passes/cmds/timeest.cc
index dbffce5e9..fb5ff1f7c 100644
--- a/passes/cmds/timeest.cc
+++ b/passes/cmds/timeest.cc
@@ -42,7 +42,7 @@ struct EstimateSta {
 	std::optional<SigBit> clk;
 	bool top_port_endpoints = false;
 
-	dict<std::pair<RTLIL::IdString, dict<RTLIL::IdString, RTLIL::Const>>, Aig> aigs;
+	dict<std::pair<RTLIL::IdString, dict<RTLIL::LeafIdString, RTLIL::Const>>, Aig> aigs;
 	dict<Cell *, Aig *> cell_aigs;
 
 	std::vector<std::pair<Cell *, SigBit>> launchers;
diff --git a/passes/cmds/viz.cc b/passes/cmds/viz.cc
index 247fd029e..094e83849 100644
--- a/passes/cmds/viz.cc
+++ b/passes/cmds/viz.cc
@@ -703,7 +703,7 @@ struct VizWorker
 
 	void update_attrs()
 	{
-		IdString vg_id = module->twines().add(std::string("\\vg"));
+		LeafIdString vg_id = module->twines().add(std::string("\\vg"));
 		for (auto c : module->cells())
 			c->attributes.erase(vg_id);
 		for (auto g : graph.nodes) {
diff --git a/passes/cmds/wrapcell.cc b/passes/cmds/wrapcell.cc
index 62c147085..cb0777659 100644
--- a/passes/cmds/wrapcell.cc
+++ b/passes/cmds/wrapcell.cc
@@ -48,7 +48,7 @@ struct ContextData {
 	std::string unused_outputs;
 };
 
-std::optional<std::string> format_with_params(const TwinePool &twines, std::string fmt, const dict<IdString, Const> &parameters,
+std::optional<std::string> format_with_params(const TwinePool &twines, std::string fmt, const dict<LeafIdString, Const> &parameters,
 								  const ContextData &context)
 {
 	std::stringstream result;
@@ -70,7 +70,7 @@ std::optional<std::string> format_with_params(const TwinePool &twines, std::stri
 				result << context.unused_outputs;
 			} else {
 				auto name = RTLIL::escape_id(std::string(beg, it));
-				IdString id = twines.find(name);
+				LeafIdString id = twines.find(name);
 				if (id == IdString::Null || !parameters.count(id)) {
 					log("Parameter %s referenced in format string '%s' not found\n", name, fmt);
 					return {};
@@ -162,10 +162,10 @@ struct WrapcellPass : Pass {
 		log_header(d, "Executing WRAPCELL pass. (wrap selected cells)\n");
 
 		struct AttrRule {
-			IdString name;
+			LeafIdString name;
 			std::string value_fmt;
 
-			AttrRule(IdString name, std::string value_fmt)
+			AttrRule(LeafIdString name, std::string value_fmt)
 				: name(name), value_fmt(value_fmt) {}
 		};
 		std::vector<AttrRule> attributes;
@@ -176,7 +176,7 @@ struct WrapcellPass : Pass {
 			if (args[argidx] == "-setattr" && argidx+1 < args.size()) {
 				attributes.emplace_back(d->twines.add(RTLIL::escape_id(args[++argidx])), "");
 			} else if (args[argidx] == "-formatattr" && argidx+2 < args.size()) {
-				IdString id = d->twines.add(RTLIL::escape_id(args[++argidx]));
+				LeafIdString id = d->twines.add(RTLIL::escape_id(args[++argidx]));
 				attributes.emplace_back(id, args[++argidx]);
 			} else if (args[argidx] == "-name" && argidx+1 < args.size()) {
 				name_fmt = args[++argidx];
diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc
index a5d1ef25e..bb3fe6b94 100644
--- a/passes/fsm/fsm_export.cc
+++ b/passes/fsm/fsm_export.cc
@@ -50,7 +50,7 @@ std::string kiss_convert_signal(const RTLIL::SigSpec &sig) {
  * @param cell pointer to the FSM cell which should be exported.
  */
 void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::string filename, bool origenc) {
-	dict<RTLIL::IdString, RTLIL::Const>::iterator attr_it;
+	dict<RTLIL::LeafIdString, RTLIL::Const>::iterator attr_it;
 	FsmData fsm_data;
 	FsmData::transition_t tr;
 	std::ofstream kiss_file;
@@ -145,7 +145,7 @@ struct FsmExportPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
-		dict<RTLIL::IdString, RTLIL::Const>::iterator attr_it;
+		dict<RTLIL::LeafIdString, RTLIL::Const>::iterator attr_it;
 		std::string arg;
 		bool flag_noauto = false;
 		std::string filename;
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index fd8c76612..174bd0cc2 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -1031,7 +1031,7 @@ struct HierarchyPass : public Pass {
 			top_mod = design->module(top_name);
 			RTLIL::Module *abstract_mod = design->module(abstract_id);
 
-			dict<RTLIL::IdString, RTLIL::Const> top_parameters;
+			dict<RTLIL::LeafIdString, RTLIL::Const> top_parameters;
 			if ((top_mod == nullptr && abstract_mod) || top_mod != nullptr) {
 				for (auto &para : parameters) {
 					SigSpec sig_value;
@@ -1123,7 +1123,7 @@ struct HierarchyPass : public Pass {
 		if (top_mod != nullptr && top_mod->name.begins_with("$abstract")) {
 			IdString top_name = design->twines.add(top_mod->name.str().substr(strlen("$abstract")));
 
-			dict<RTLIL::IdString, RTLIL::Const> top_parameters;
+			dict<RTLIL::LeafIdString, RTLIL::Const> top_parameters;
 			for (auto &para : parameters) {
 				SigSpec sig_value;
 				if (!RTLIL::SigSpec::parse(sig_value, NULL, para.second))
@@ -1273,7 +1273,7 @@ struct HierarchyPass : public Pass {
 					}
 				}
 
-				pool<std::pair<IdString, IdString>> params_rename;
+				pool<std::pair<LeafIdString, LeafIdString>> params_rename;
 				for (const auto &p : cell->parameters) {
 					int id;
 					if (read_id_num(*design, p.first, &id)) {
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc
index 01c3f8132..3cd8a0303 100644
--- a/passes/memory/memory_bram.cc
+++ b/passes/memory/memory_bram.cc
@@ -97,7 +97,7 @@ struct rules_t
 			return portinfos;
 		}
 
-		void find_variant_params(TwinePool &twines, dict<IdString, Const> &variant_params, const bram_t &other) const
+		void find_variant_params(TwinePool &twines, dict<LeafIdString, Const> &variant_params, const bram_t &other) const
 		{
 			log_assert(name == other.name);
 
@@ -135,7 +135,7 @@ struct rules_t
 		dict<string, int> min_limits, max_limits;
 		bool or_next_if_better, make_transp, make_outreg;
 		char shuffle_enable;
-		vector<vector<std::tuple<bool,IdString,Const>>> attributes;
+		vector<vector<std::tuple<bool,LeafIdString,Const>>> attributes;
 	};
 
 	bool attr_icase;
@@ -352,7 +352,7 @@ struct rules_t
 					size_t c1 = tokens[idx][0] == '!' ? 1 : 0;
 					size_t c2 = tokens[idx].find("=");
 					bool exists = (c1 == 0);
-					IdString key = design->twines.add(RTLIL::escape_id(tokens[idx].substr(c1, c2)));
+					LeafIdString key = design->twines.add(RTLIL::escape_id(tokens[idx].substr(c1, c2)));
 					Const val = c2 != std::string::npos ? tokens[idx].substr(c2+1) : RTLIL::Const(1);
 
 					data.attributes.back().emplace_back(exists, key, map_case(val));
@@ -741,7 +741,7 @@ grow_read_ports:;
 			bool found = false;
 			for (const auto &term : sums) {
 				bool exists = std::get<0>(term);
-				IdString key = std::get<1>(term);
+				LeafIdString key = std::get<1>(term);
 				const Const &value = std::get<2>(term);
 				auto it = mem.attributes.find(key);
 				if (it == mem.attributes.end()) {
@@ -864,7 +864,7 @@ grow_read_ports:;
 
 	// prepare variant parameters
 
-	dict<IdString, Const> variant_params;
+	dict<LeafIdString, Const> variant_params;
 	for (auto &other_bram : rules.brams.at(bram.name))
 		bram.find_variant_params(module->twines(), variant_params, other_bram);
 
@@ -1119,7 +1119,7 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
 				bool found = false;
 				for (const auto &term : sums) {
 					bool exists = std::get<0>(term);
-					IdString key = std::get<1>(term);
+					LeafIdString key = std::get<1>(term);
 					const Const &value = std::get<2>(term);
 					auto it = mem.attributes.find(key);
 					if (it == mem.attributes.end()) {
diff --git a/passes/memory/memory_libmap.cc b/passes/memory/memory_libmap.cc
index 5a7387e2e..aedad3778 100644
--- a/passes/memory/memory_libmap.cc
+++ b/passes/memory/memory_libmap.cc
@@ -487,7 +487,7 @@ void MemMapping::dump_config(MemConfig &cfg) {
 	}
 }
 
-std::pair<bool, Const> search_for_attribute(Mem mem, IdString attr) {
+std::pair<bool, Const> search_for_attribute(Mem mem, LeafIdString attr) {
 	// priority of attributes:
 	// 1. attributes on memory itself
 	// 2. attributes on a read or write port
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
index f5183296f..7910321c1 100644
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@ -118,7 +118,7 @@ struct MemoryMapWorker
 
 		// check if attributes allow us to infer FFRAM for this memory
 		for (const auto &attr : attributes) {
-			IdString attr_ref = design->twines.find(attr.first);
+			LeafIdString attr_ref = design->twines.find(attr.first);
 			if (attr_ref != IdString::Null && mem.attributes.count(attr_ref)) {
 				const auto &cell_attr = mem.attributes[attr_ref];
 				if (attr.second.empty()) {
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 6d570d774..83d98b89b 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -303,7 +303,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
 	return true;
 }
 
-void handle_polarity_inv(Cell *cell, IdString port, IdString param, const SigMap &assign_map, const dict<RTLIL::SigSpec, RTLIL::SigSpec> &invert_map)
+void handle_polarity_inv(Cell *cell, IdString port, LeafIdString param, const SigMap &assign_map, const dict<RTLIL::SigSpec, RTLIL::SigSpec> &invert_map)
 {
 	SigSpec sig = assign_map(cell->getPort(port));
 	if (invert_map.count(sig)) {
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index 42109a9b9..d4e11da7e 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -152,7 +152,7 @@ bool decode_port_signed(RTLIL::Cell *cell, RTLIL::IdString port_name)
 	if (cell->type.in(BITWISE_OPS, LOGICAL_OPS))
 		return false;
 
-	RTLIL::IdString param_name = port_name == ID::A ? ID::A_SIGNED : ID::B_SIGNED;
+	RTLIL::LeafIdString param_name = port_name == ID::A ? ID::A_SIGNED : ID::B_SIGNED;
 	if (cell->hasParam(param_name))
 		return cell->getParam(param_name).as_bool();
 
diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py
index c6243be4c..07c9204da 100644
--- a/passes/pmgen/pmgen.py
+++ b/passes/pmgen/pmgen.py
@@ -417,9 +417,9 @@ with open(outfile, "w") as f:
 
     for v, n in sorted(ids.items()):
         if n[0] == "\\":
-            print("  IdString {}{{ID::{}}};".format(v, n[1:]), file=f)
+            print("  LeafIdString {}{{ID::{}}};".format(v, n[1:]), file=f)
         else:
-            print("  IdString {}{{ID::{}}};".format(v, n), file=f)
+            print("  LeafIdString {}{{ID::{}}};".format(v, n), file=f)
     print("", file=f)
 
     print("  void add_siguser(const SigSpec &sig, Cell *cell) {", file=f)
@@ -462,13 +462,13 @@ with open(outfile, "w") as f:
     print("  }", file=f)
     print("", file=f)
 
-    print("  Const param(Cell *cell, IdString paramname) {", file=f)
+    print("  Const param(Cell *cell, LeafIdString paramname) {", file=f)
     print("    try {", file=f)
     print("      return cell->getParam(paramname);", file=f)
     print("    } catch(std::out_of_range&) { log_error(\"Accessing non existing parameter %s\\n\", PooledName(module, paramname).unescape()); }", file=f)
     print("  }", file=f)
     print("", file=f)
-    print("  Const param(Cell *cell, IdString paramname, const Const& defval) {", file=f)
+    print("  Const param(Cell *cell, LeafIdString paramname, const Const& defval) {", file=f)
     print("    return cell->parameters.at(paramname, defval);", file=f)
     print("  }", file=f)
     print("", file=f)
diff --git a/passes/sat/formalff.cc b/passes/sat/formalff.cc
index a2500bde4..dc374e330 100644
--- a/passes/sat/formalff.cc
+++ b/passes/sat/formalff.cc
@@ -53,7 +53,7 @@ struct InitValWorker
 	}
 
 	// Sign/Zero-extended indexing of individual port bits
-	static SigBit bit_in_port(RTLIL::Cell *cell, RTLIL::IdString port, RTLIL::IdString sign, int index)
+	static SigBit bit_in_port(RTLIL::Cell *cell, RTLIL::IdString port, RTLIL::LeafIdString sign, int index)
 	{
 		auto sig_port = cell->getPort(port);
 		if (index < GetSize(sig_port))
diff --git a/passes/techmap/attrmap.cc b/passes/techmap/attrmap.cc
index fccf25560..466042c48 100644
--- a/passes/techmap/attrmap.cc
+++ b/passes/techmap/attrmap.cc
@@ -118,9 +118,9 @@ struct AttrmapRemove : AttrmapAction {
 	}
 };
 
-void attrmap_apply(RTLIL::Design *design, string objname, vector<std::unique_ptr<AttrmapAction>> &actions, dict<IdString, RTLIL::Const> &attributes)
+void attrmap_apply(RTLIL::Design *design, string objname, vector<std::unique_ptr<AttrmapAction>> &actions, dict<LeafIdString, RTLIL::Const> &attributes)
 {
-	dict<RTLIL::IdString, RTLIL::Const> new_attributes;
+	dict<RTLIL::LeafIdString, RTLIL::Const> new_attributes;
 
 	for (auto attr : attributes)
 	{
diff --git a/passes/techmap/attrmvcp.cc b/passes/techmap/attrmvcp.cc
index 2d879ff0d..02d5c33d6 100644
--- a/passes/techmap/attrmvcp.cc
+++ b/passes/techmap/attrmvcp.cc
@@ -107,7 +107,7 @@ struct AttrmvcpPass : public Pass {
 
 			for (auto wire : module->selected_wires())
 			{
-				dict<IdString, Const> new_attributes;
+				dict<LeafIdString, Const> new_attributes;
 
 				for (auto attr : wire->attributes)
 				{
diff --git a/passes/techmap/constmap.cc b/passes/techmap/constmap.cc
index c1cb49db4..2b10fb46d 100644
--- a/passes/techmap/constmap.cc
+++ b/passes/techmap/constmap.cc
@@ -25,7 +25,8 @@ USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
 static std::string celltype, cell_portname, cell_paramname;
-static IdString celltype_ref, cell_portname_ref, cell_paramname_ref;
+static IdString celltype_ref, cell_portname_ref;
+static LeafIdString cell_paramname_ref;
 
 static RTLIL::Module *module;
 static RTLIL::SigChunk value;
diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc
index 8d8bdc362..3ec5f52bf 100644
--- a/passes/techmap/dffinit.cc
+++ b/passes/techmap/dffinit.cc
@@ -59,7 +59,7 @@ struct DffinitPass : public Pass {
 	{
 		log_header(design, "Executing DFFINIT pass (set INIT param on FF cells).\n");
 
-		dict<IdString, dict<IdString, IdString>> ff_types;
+		dict<IdString, dict<IdString, LeafIdString>> ff_types;
 		bool highlow_mode = false, noreinit = false;
 		std::string high_string, low_string;
 
@@ -81,7 +81,7 @@ struct DffinitPass : public Pass {
 				TwineSearch search(&design->twines);
 				IdString cell_name = search.find(RTLIL::escape_id(args[++argidx]));
 				IdString output_port = search.find(RTLIL::escape_id(args[++argidx]));
-				IdString init_param = search.find(RTLIL::escape_id(args[++argidx]));
+				LeafIdString init_param = design->twines.add(RTLIL::escape_id(args[++argidx]));
 				ff_types[cell_name][output_port] = init_param;
 				continue;
 			}
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index b94a41409..0c486a6f0 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -462,7 +462,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
 		IdString cell_type = cell->type;
 		IdString cell_name = cell->name;
 		auto cell_connections = cell->connections();
-		dict<RTLIL::IdString, RTLIL::Const> attributes = std::move(cell->attributes);
+		dict<RTLIL::LeafIdString, RTLIL::Const> attributes = std::move(cell->attributes);
 
 		module->remove(cell);
 
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index df991058a..599a9f3de 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -34,13 +34,13 @@ class SubCircuitSolver : public SubCircuit::Solver
 public:
 	bool ignore_parameters;
 	std::set<std::pair<RTLIL::IdString, RTLIL::IdString>> ignored_parameters;
-	std::set<RTLIL::IdString> cell_attr, wire_attr;
+	std::set<RTLIL::LeafIdString> cell_attr, wire_attr;
 
 	SubCircuitSolver() : ignore_parameters(false)
 	{
 	}
 
-	bool compareAttributes(const std::set<RTLIL::IdString> &attr, const dict<RTLIL::IdString, RTLIL::Const> &needleAttr, const dict<RTLIL::IdString, RTLIL::Const> &haystackAttr)
+	bool compareAttributes(const std::set<RTLIL::LeafIdString> &attr, const dict<RTLIL::LeafIdString, RTLIL::Const> &needleAttr, const dict<RTLIL::LeafIdString, RTLIL::Const> &haystackAttr)
 	{
 		for (auto &it : attr) {
 			size_t nc = needleAttr.count(it), hc = haystackAttr.count(it);
@@ -124,7 +124,7 @@ public:
 		{
 			RTLIL::Wire *lastNeedleWire = nullptr;
 			RTLIL::Wire *lastHaystackWire = nullptr;
-			dict<RTLIL::IdString, RTLIL::Const> emptyAttr;
+			dict<RTLIL::LeafIdString, RTLIL::Const> emptyAttr;
 
 			for (auto &conn : needleCell->connections())
 			{
diff --git a/passes/techmap/extractinv.cc b/passes/techmap/extractinv.cc
index 084d9d5cc..7d0481d58 100644
--- a/passes/techmap/extractinv.cc
+++ b/passes/techmap/extractinv.cc
@@ -97,7 +97,7 @@ struct ExtractinvPass : public Pass {
 				auto it = cell_wire->attributes.find(ID::invertible_pin);
 				if (it == cell_wire->attributes.end())
 					continue;
-				IdString param_name = design->twines.find(RTLIL::escape_id(it->second.decode_string()));
+				LeafIdString param_name = design->twines.find(RTLIL::escape_id(it->second.decode_string()));
 				auto it2 = cell->parameters.find(param_name);
 				// Inversion not used -- skip.
 				if (it2 == cell->parameters.end())
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index 2c252deb3..db752fb21 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -27,7 +27,7 @@
 USING_YOSYS_NAMESPACE
 YOSYS_NAMESPACE_BEGIN
 
-static void transfer_attr (Cell* to, const Cell* from, IdString attr) {
+static void transfer_attr (Cell* to, const Cell* from, LeafIdString attr) {
 	if (from->has_attribute(attr))
 		to->attributes[attr] = from->attributes.at(attr);
 }
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index e29ac831a..0365bd692 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -109,7 +109,7 @@ static RTLIL::Wire *map_port(RTLIL::Module *tpl, RTLIL::Design *src, IdString na
 struct TechmapWorker
 {
 	dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
-	dict<std::pair<IdString, dict<IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
+	dict<std::pair<IdString, dict<LeafIdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
 	dict<RTLIL::Module*, bool> techmap_do_cache;
 	pool<RTLIL::Module*> module_queue;
 	dict<Module*, SigMap> sigmaps;
@@ -532,7 +532,7 @@ struct TechmapWorker
 			{
 				IdString derived_name = tpl_name;
 				RTLIL::Module *tpl = map->module(derived_name);
-				dict<IdString, RTLIL::Const> parameters;
+				dict<LeafIdString, RTLIL::Const> parameters;
 				for (auto &p : cell->parameters)
 					parameters[map->twines.copy_from(design->twines, p.first)] = p.second;
 
@@ -662,7 +662,8 @@ struct TechmapWorker
 					RTLIL::Wire *tpl_port = map_port(tpl, design, conn.first);
 					if (tpl_port != nullptr && tpl_port->port_id > 0)
 						continue;
-					IdString conn_id = map->twines.copy_from(design->twines, conn.first);
+					// Constant ports are passed as the template parameter of the same name
+					LeafIdString conn_id = map->twines.flatten(map->twines.copy_from(design->twines, conn.first));
 					if (!conn.second.is_fully_const() || parameters.count(conn_id) > 0 || tpl->avail_parameters.count(conn_id) == 0)
 						goto next_tpl;
 					parameters[conn_id] = conn.second.as_const();
@@ -741,7 +742,7 @@ struct TechmapWorker
 			use_wrapper_tpl:;
 					// do not register techmap_wrap modules with techmap_cache
 				} else {
-					std::pair<IdString, dict<IdString, RTLIL::Const>> key(tpl_name, parameters);
+					std::pair<IdString, dict<LeafIdString, RTLIL::Const>> key(tpl_name, parameters);
 					auto it = techmap_cache.find(key);
 					if (it != techmap_cache.end()) {
 						tpl = it->second;
diff --git a/techlibs/gatemate/gatemate_foldinv.cc b/techlibs/gatemate/gatemate_foldinv.cc
index 2843d62eb..800532447 100644
--- a/techlibs/gatemate/gatemate_foldinv.cc
+++ b/techlibs/gatemate/gatemate_foldinv.cc
@@ -26,7 +26,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct LUTPin {
     int input_bit;
-    IdString init_param;
+    LeafIdString init_param;
 };
 
 struct LUTType {
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 25b7d927f..c64ebd50a 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -118,7 +118,7 @@ static void run_ice40_opts(Module *module)
 			if (GetSize(replacement_output)) {
 				optimized_co.insert(sigmap(cell->getPort(ID::CO)[0]));
 				TwinePool &twines = module->twines();
-				IdString lut_name_attr = twines.add(std::string("\\SB_LUT4.name"));
+				LeafIdString lut_name_attr = twines.add(std::string("\\SB_LUT4.name"));
 				auto it = cell->attributes.find(lut_name_attr);
 				if (it != cell->attributes.end()) {
 					module->rename(cell, it->second.decode_string());
diff --git a/techlibs/ice40/ice40_wrapcarry.cc b/techlibs/ice40/ice40_wrapcarry.cc
index 1538767da..9ef612dd6 100644
--- a/techlibs/ice40/ice40_wrapcarry.cc
+++ b/techlibs/ice40/ice40_wrapcarry.cc
@@ -124,7 +124,7 @@ struct Ice40WrapCarryPass : public Pass {
 					carry->setPort(ID::CO, cell->getPort(ID::CO));
 					module->swap_names(carry, cell);
 					TwinePool &twines = module->twines();
-					IdString lut_name_attr = twines.add(std::string("\\SB_LUT4.name"));
+					LeafIdString lut_name_attr = twines.add(std::string("\\SB_LUT4.name"));
 					auto lut_name = cell->attributes.find(lut_name_attr);
 					auto lut = lut_name != cell->attributes.end()
 						? module->addCell(lut_name->second.decode_string(), ID($lut))
diff --git a/techlibs/lattice/lattice_dsp_nexus.pmg b/techlibs/lattice/lattice_dsp_nexus.pmg
index 8b75baf14..f6ce93e9e 100644
--- a/techlibs/lattice/lattice_dsp_nexus.pmg
+++ b/techlibs/lattice/lattice_dsp_nexus.pmg
@@ -95,8 +95,8 @@ code
 		Cell *mac = module->addCell(NEW_ID, "$__NX_PREADD18X18");
 
 		IdString mul_other = (actual_mul_AB == \A) ? \B : \A;
-		IdString sgn_AC = (mul_other == \A) ? \B_SIGNED : \A_SIGNED;
-		IdString sgn_B = (mul_other == \A) ? \A_SIGNED : \B_SIGNED;
+		LeafIdString sgn_AC = (mul_other == \A) ? \B_SIGNED : \A_SIGNED;
+		LeafIdString sgn_B = (mul_other == \A) ? \A_SIGNED : \B_SIGNED;
 
 		SigSpec sig_A = port(preadd, \A);
 		SigSpec sig_C = port(preadd, \B);
diff --git a/techlibs/quicklogic/ql_bram_merge.cc b/techlibs/quicklogic/ql_bram_merge.cc
index 241ff7f64..7ea86c989 100644
--- a/techlibs/quicklogic/ql_bram_merge.cc
+++ b/techlibs/quicklogic/ql_bram_merge.cc
@@ -32,7 +32,7 @@ PRIVATE_NAMESPACE_BEGIN
 struct QlBramMergeWorker {
 
 	// can be used to record parameter values that have to match on both sides
-	typedef dict<RTLIL::IdString, RTLIL::Const> MergeableGroupKeyType;
+	typedef dict<RTLIL::LeafIdString, RTLIL::Const> MergeableGroupKeyType;
 
 	RTLIL::Module *module;
 	dict<MergeableGroupKeyType, pool<RTLIL::Cell*>> mergeable_groups;
@@ -58,16 +58,16 @@ struct QlBramMergeWorker {
 		return key;
 	}
 
-	const dict<RTLIL::IdString, RTLIL::IdString>& param_map(bool second)
+	const dict<RTLIL::LeafIdString, RTLIL::LeafIdString>& param_map(bool second)
 	{
-		static const dict<RTLIL::IdString, RTLIL::IdString> bram1_map = {
+		static const dict<RTLIL::LeafIdString, RTLIL::LeafIdString> bram1_map = {
 			{ ID(INIT),                     ID(INIT1) },
 			{ ID(PORT_A_WIDTH),             ID(PORT_A1_WIDTH) },
 			{ ID(PORT_B_WIDTH),             ID(PORT_B1_WIDTH) },
 			{ ID(PORT_A_WR_BE_WIDTH),       ID(PORT_A1_WR_BE_WIDTH) },
 			{ ID(PORT_B_WR_BE_WIDTH),       ID(PORT_B1_WR_BE_WIDTH) }
 		};
-		static const dict<RTLIL::IdString, RTLIL::IdString> bram2_map = {
+		static const dict<RTLIL::LeafIdString, RTLIL::LeafIdString> bram2_map = {
 			{ ID(INIT),                     ID(INIT2) },
 			{ ID(PORT_A_WIDTH),             ID(PORT_A2_WIDTH) },
 			{ ID(PORT_B_WIDTH),             ID(PORT_B2_WIDTH) },
@@ -81,9 +81,9 @@ struct QlBramMergeWorker {
 			return bram1_map;
 	}
 
-	const dict<RTLIL::IdString, RTLIL::IdString>& port_map(bool second)
+	const dict<RTLIL::LeafIdString, RTLIL::LeafIdString>& port_map(bool second)
 	{
-		static const dict<RTLIL::IdString, RTLIL::IdString> bram1_map = {
+		static const dict<RTLIL::LeafIdString, RTLIL::LeafIdString> bram1_map = {
 			{ ID(PORT_A_CLK),       ID(PORT_A1_CLK) },
 			{ ID(PORT_B_CLK),       ID(PORT_B1_CLK) },
 			{ ID(PORT_A_CLK_EN),    ID(PORT_A1_CLK_EN) },
@@ -99,7 +99,7 @@ struct QlBramMergeWorker {
 			{ ID(PORT_A_RD_DATA),   ID(PORT_A1_RD_DATA) },
 			{ ID(PORT_B_RD_DATA),   ID(PORT_B1_RD_DATA) }
 		};
-		static const dict<RTLIL::IdString, RTLIL::IdString> bram2_map = {
+		static const dict<RTLIL::LeafIdString, RTLIL::LeafIdString> bram2_map = {
 			{ ID(PORT_A_CLK),       ID(PORT_A2_CLK) },
 			{ ID(PORT_B_CLK),       ID(PORT_B2_CLK) },
 			{ ID(PORT_A_CLK_EN),    ID(PORT_A2_CLK_EN) },
diff --git a/techlibs/quicklogic/ql_dsp_simd.cc b/techlibs/quicklogic/ql_dsp_simd.cc
index 0101eae69..ec624220b 100644
--- a/techlibs/quicklogic/ql_dsp_simd.cc
+++ b/techlibs/quicklogic/ql_dsp_simd.cc
@@ -197,7 +197,7 @@ struct QlDspSimdPass : public Pass {
 					// MODE_BITS parameter
 					Const mode_bits;
 					for (const auto &it : m_DspParams) {
-						IdString param = module->twines().add("\\" + it);
+						LeafIdString param = module->twines().add("\\" + it);
 						auto val_a = dsp_a->getParam(param);
 						auto val_b = dsp_b->getParam(param);
 
diff --git a/tests/rtlil/twine_suffix_attr.ys b/tests/rtlil/twine_suffix_attr.ys
new file mode 100644
index 000000000..13e1f1cb5
--- /dev/null
+++ b/tests/rtlil/twine_suffix_attr.ys
@@ -0,0 +1,12 @@
+# Attribute names are leaf twines, Yosys never writes them as suffix twines
+logger -expect error "Expected leaf twine for attribute or parameter name, got suffix twine `\\keep'" 1
+read_rtlil <<EOT
+twines
+  leaf 100000 "kee"
+  suffix 100001 100000 "p"
+end
+module \top
+  attribute $pub@100001 1
+  wire \w
+end
+EOT
diff --git a/tests/rtlil/twine_suffix_param.ys b/tests/rtlil/twine_suffix_param.ys
new file mode 100644
index 000000000..722c2eb3a
--- /dev/null
+++ b/tests/rtlil/twine_suffix_param.ys
@@ -0,0 +1,18 @@
+# Parameter names are leaf twines, Yosys never writes them as suffix twines
+logger -expect error "Expected leaf twine for attribute or parameter name, got suffix twine `\\WIDTH'" 1
+read_rtlil <<EOT
+twines
+  leaf 100000 "WID"
+  suffix 100001 100000 "TH"
+end
+module \sub
+  wire input 1 \a
+end
+module \top
+  wire input 1 \w
+  cell \sub \u
+    parameter $pub@100001 4
+    connect \a \w
+  end
+end
+EOT