From 9724afae7f2e02325aa50dc80de0fef1a9b7e82e Mon Sep 17 00:00:00 2001
From: nella <simontupy64@gmail.com>
Date: Wed, 30 Sep 2026 13:36:08 +0200
Subject: [PATCH] Check loops through barriers.

---
 passes/cmds/check.cc            |  2 +-
 tests/various/barrier_opaque.ys | 11 +++++++++++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc
index 3006af658..213969ab5 100644
--- a/passes/cmds/check.cc
+++ b/passes/cmds/check.cc
@@ -342,7 +342,7 @@ struct CheckPass : public Pass {
 					}
 				}
 
-				if (yosys_celltypes.cell_evaluable(cell->type) || cell->type.in(ID($mem_v2), ID($memrd), ID($memrd_v2)) \
+				if (yosys_celltypes.cell_evaluable(cell->type) || cell->type.in(ID($mem_v2), ID($memrd), ID($memrd_v2), ID($barrier)) \
 						|| cell->is_builtin_ff()) {
 					if (!edges_db.add_edges_from_cell(cell))
 						coarsened_cells.insert(cell);
diff --git a/tests/various/barrier_opaque.ys b/tests/various/barrier_opaque.ys
index 7f69798a7..3903eea2e 100644
--- a/tests/various/barrier_opaque.ys
+++ b/tests/various/barrier_opaque.ys
@@ -145,3 +145,14 @@ select -assert-count 1 t:$mux
 select -assert-count 0 w:d %co1:+[A] t:$mux %i
 design -reset
 
+# check loop
+read_verilog -icells <<EOT
+module top(output w);
+	wire n;
+	\$barrier #(.WIDTH(1)) bar (.A(n), .Y(w));
+	assign n = ~w;
+endmodule
+EOT
+logger -expect warning "found logic loop" 1
+check
+logger -check-expected