diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc
index b09184034..eaac9614d 100644
--- a/backends/blif/blif.cc
+++ b/backends/blif/blif.cc
@@ -69,13 +69,13 @@ static IdString match_port(RTLIL::Cell *cell, const std::string &escaped_name)
 
 void BlifDumperConfig::resolve(RTLIL::Design *design)
 {
-	if (RTLIL::Module *module = RTLIL::module_by_name(design, buf_type))
+	if (RTLIL::Module *module = design->module(design->twines.find(RTLIL::escape_id(buf_type))))
 		buf_module = module;
-	if (RTLIL::Module *module = RTLIL::module_by_name(design, true_type))
+	if (RTLIL::Module *module = design->module(design->twines.find(RTLIL::escape_id(true_type))))
 		true_module = module;
-	if (RTLIL::Module *module = RTLIL::module_by_name(design, false_type))
+	if (RTLIL::Module *module = design->module(design->twines.find(RTLIL::escape_id(false_type))))
 		false_module = module;
-	if (RTLIL::Module *module = RTLIL::module_by_name(design, undef_type))
+	if (RTLIL::Module *module = design->module(design->twines.find(RTLIL::escape_id(undef_type))))
 		undef_module = module;
 
 	std::vector<std::array<std::string, 3>> escaped_unbuf;
diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 483304a7c..ecc34596b 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -79,7 +79,6 @@ struct BtorWorker
 	dict<SigBit, bool> initbits;
 	pool<Wire*> statewires;
 	pool<string> srcsymbols;
-	std::optional<pool<string>> module_names;
 	vector<Mem> memories;
 	dict<Cell*, Mem*> mem_cells;
 
@@ -119,11 +118,7 @@ struct BtorWorker
 
 	bool srcsym_taken(const string &sym)
 	{
-		if (srcsymbols.count(sym))
-			return true;
-		if (!module_names)
-			module_names = RTLIL::object_names(module);
-		return module_names->count("\\" + sym) != 0;
+		return srcsymbols.count(sym) || module->count_id(module->twines().find("\\" + sym));
 	}
 
 	string uniquify_srcsym(string src)
diff --git a/backends/smv/smv.cc b/backends/smv/smv.cc
index 50c5ec3e5..c5fe8a7f7 100644
--- a/backends/smv/smv.cc
+++ b/backends/smv/smv.cc
@@ -791,7 +791,7 @@ struct SmvBackend : public Backend {
 
 					if (GetSize(stmt) == 2 && stmt[0] == "%module")
 					{
-						Module *module = RTLIL::module_by_name(design, stmt[1]);
+						Module *module = design->module(design->twines.find(RTLIL::escape_id(stmt[1])));
 						modules.erase(module);
 
 						if (module == nullptr)
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 93074d1de..d73f3c9f3 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -103,7 +103,6 @@ std::set<RTLIL::IdString> reg_wires;
 std::string auto_prefix, extmem_prefix;
 
 RTLIL::Module *active_module;
-pool<std::string> active_object_names;
 dict<RTLIL::SigBit, RTLIL::State> active_initdata;
 SigMap active_sigmap;
 std::string initial_id;
@@ -143,7 +142,6 @@ void reset_auto_counter(RTLIL::Module *module)
 	auto_name_map.clear();
 	auto_name_counter = 0;
 	auto_name_offset = 0;
-	active_object_names = RTLIL::object_names(module);
 
 	reset_auto_counter_id(module->name, false);
 
@@ -1087,7 +1085,7 @@ std::string cellname(RTLIL::Cell *cell)
 		if (wire->width != 1)
 			cell_name += stringf("[%d]", wire->start_offset + sig[0].offset);
 
-		if (active_module && active_object_names.count(cell_name))
+		if (active_module && active_module->count_id(active_module->twines().find(cell_name)) > 0)
 				goto no_special_reg_name;
 
 		return id(cell_name);
@@ -2550,7 +2548,6 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 
 	f << stringf("%s" "endmodule\n", indent);
 	active_module = NULL;
-	active_object_names.clear();
 	active_sigmap.clear();
 	active_initdata.clear();
 }
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index e2c59c301..45598181d 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1050,17 +1050,6 @@ RTLIL::Module *RTLIL::Design::module(IdString id) {
 	return modules_.count(id) ? modules_.at(id) : NULL;
 }
 
-RTLIL::Module *RTLIL::module_by_name(RTLIL::Design *design, const std::string &name)
-{
-	if (name.empty())
-		return nullptr;
-	std::string escaped = escape_id(name);
-	for (auto module : design->modules())
-		if (design->twines.name_equal(module->name, escaped))
-			return module;
-	return nullptr;
-}
-
 RTLIL::Module *RTLIL::Design::top_module() const
 {
 	RTLIL::Module *module = nullptr;
@@ -1452,21 +1441,6 @@ size_t RTLIL::Module::count_id(RTLIL::IdString id)
 	return wires_.count(id) + cells_.count(id) + memories.count(id) + processes.count(id);
 }
 
-pool<std::string> RTLIL::object_names(const RTLIL::Module *module)
-{
-	const TwinePool &twines = module->twines();
-	pool<std::string> names;
-	for (auto &it : module->wires_)
-		names.insert(twines.str(it.first));
-	for (auto &it : module->cells_)
-		names.insert(twines.str(it.first));
-	for (auto &it : module->memories)
-		names.insert(twines.str(it.first));
-	for (auto &it : module->processes)
-		names.insert(twines.str(it.first));
-	return names;
-}
-
 #ifndef NDEBUG
 namespace {
 	struct InternalCellChecker
@@ -1560,10 +1534,8 @@ namespace {
 
 		void check()
 		{
-			std::string type_str = cell->type.str();
-			std::string_view type_sv = type_str;
-			if (!type_sv.starts_with("$") || type_sv.starts_with("$__") || type_sv.starts_with("$paramod") || type_sv.starts_with("$fmcombine") ||
-					type_sv.starts_with("$verific$") || type_sv.starts_with("$array:") || type_sv.starts_with("$extern:"))
+			if (cell->type.isPublic() || cell->type.begins_with("$__") || cell->type.begins_with("$paramod") || cell->type.begins_with("$fmcombine") ||
+					cell->type.begins_with("$verific$") || cell->type.begins_with("$array:") || cell->type.begins_with("$extern:"))
 				return;
 
 			if (cell->type == ID($buf)) {
@@ -3084,17 +3056,6 @@ void RTLIL::copy_attr_dict(dict<IdString, RTLIL::Const> &dst,
 	}
 }
 
-RTLIL::Wire *RTLIL::wire_by_name(RTLIL::Module *module, const std::string &name)
-{
-	if (name.empty())
-		return nullptr;
-	std::string escaped = escape_id(name);
-	for (auto wire : module->wires())
-		if (module->twines().name_equal(wire->name, escaped))
-			return wire;
-	return nullptr;
-}
-
 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
 {
 	log_assert(design);
@@ -4419,10 +4380,8 @@ void RTLIL::Cell::check()
 
 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
 {
-	std::string type_str = type.str();
-	std::string_view type_sv = type_str;
-	if (!type_sv.starts_with("$") || type_sv.starts_with("$_") || type_sv.starts_with("$paramod") || type_sv.starts_with("$fmcombine") ||
-			type_sv.starts_with("$verific$") || type_sv.starts_with("$array:") || type_sv.starts_with("$extern:"))
+	if (type.isPublic() || type.begins_with("$_") || type.begins_with("$paramod") || type.begins_with("$fmcombine") ||
+			type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:"))
 		return;
 
 	if (type == ID($buf) || type == ID($mux) || type == ID($pmux) || type == ID($bmux) || type == ID($bwmux) || type == ID($bweqx)) {
diff --git a/kernel/rtlil_twine_compat.h b/kernel/rtlil_twine_compat.h
index 7f3fb5f43..c596eef94 100644
--- a/kernel/rtlil_twine_compat.h
+++ b/kernel/rtlil_twine_compat.h
@@ -106,10 +106,6 @@ private:
 	Owner *owner() { return const_cast<Owner *>(static_cast<const IdFieldMasq *>(this)->owner()); }
 };
 
-Module *module_by_name(Design *design, const std::string &name);
-Wire *wire_by_name(Module *module, const std::string &name);
-pool<std::string> object_names(const Module *module);
-
 struct PooledName : IdMasqBase<PooledName> {
 	PooledName() = default;
 	explicit PooledName(IdString id) : id_(id) {}
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 4915b11b9..89fdc020b 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -986,14 +986,14 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module
 			clk_polarity = false;
 			clk_str = clk_str.substr(1);
 		}
-		if (RTLIL::Wire *wire = RTLIL::wire_by_name(module, clk_str))
+		if (RTLIL::Wire *wire = module->wire(module->twines().find(RTLIL::escape_id(clk_str))))
 			clk_sig = assign_map(wire);
 		if (en_str != "") {
 			if (en_str[0] == '!') {
 				en_polarity = false;
 				en_str = en_str.substr(1);
 			}
-			if (RTLIL::Wire *wire = RTLIL::wire_by_name(module, en_str))
+			if (RTLIL::Wire *wire = module->wire(module->twines().find(RTLIL::escape_id(en_str))))
 				en_sig = assign_map(wire);
 		}
 		if (arst_str != "") {
@@ -1001,7 +1001,7 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module
 				arst_polarity = false;
 				arst_str = arst_str.substr(1);
 			}
-			if (RTLIL::Wire *wire = RTLIL::wire_by_name(module, arst_str))
+			if (RTLIL::Wire *wire = module->wire(module->twines().find(RTLIL::escape_id(arst_str))))
 				arst_sig = assign_map(wire);
 		}
 		if (srst_str != "") {
@@ -1009,7 +1009,7 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module
 				srst_polarity = false;
 				srst_str = srst_str.substr(1);
 			}
-			if (RTLIL::Wire *wire = RTLIL::wire_by_name(module, srst_str))
+			if (RTLIL::Wire *wire = module->wire(module->twines().find(RTLIL::escape_id(srst_str))))
 				srst_sig = assign_map(wire);
 		}
 	}
diff --git a/tests/unit/kernel/twinePublicityTest.cc b/tests/unit/kernel/twinePublicityTest.cc
index 2b632ef44..0b3fcdc28 100644
--- a/tests/unit/kernel/twinePublicityTest.cc
+++ b/tests/unit/kernel/twinePublicityTest.cc
@@ -101,7 +101,7 @@ TEST(TwinePublicityTest, SearchPublicity)
 	ASSERT_EQ(priv, pub.untag());
 
 	IdString found_pub = pool.find(std::string_view("\\sig"));
-	IdString found_priv = pool.find(std::string_view("sig"));
+	IdString found_priv = pool.find(TwineSpec::Leaf{"sig"});
 
 	EXPECT_TRUE(found_pub.isPublic());
 	EXPECT_FALSE(found_priv.isPublic());