diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc
index b449660a9..f78da20c0 100644
--- a/passes/opt/muxpack.cc
+++ b/passes/opt/muxpack.cc
@@ -294,7 +294,6 @@ struct MuxpackWorker
 					s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort(ID::S)));
 				}
 				remove_cells.insert(cursor_cell);
-				first_cell->add_strpool_attribute(ID::src, cursor_cell->get_strpool_attribute(ID::src));
 			}
 
 			first_cell->setPort(ID::B, b_sig);
diff --git a/tests/opt/muxpack_src.ys b/tests/opt/muxpack_src.ys
deleted file mode 100644
index 48b3b07e9..000000000
--- a/tests/opt/muxpack_src.ys
+++ /dev/null
@@ -1,57 +0,0 @@
-read_rtlil <<EOT
-module \top
-  wire width 2 input 1 \a
-  wire width 2 input 2 \b
-  wire width 2 input 3 \c
-  wire input 4 \sel
-  wire \eq0_y
-  wire \eq1_y
-  wire width 2 \mux0_y
-  wire width 2 output 5 \y
-
-  cell $eq \eq0
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \sel
-    connect \B 1'0
-    connect \Y \eq0_y
-  end
-
-  cell $eq \eq1
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \sel
-    connect \B 1'1
-    connect \Y \eq1_y
-  end
-
-  attribute \src "muxpack_src_a"
-  cell $mux \mux0
-    parameter \WIDTH 2
-    connect \A \a
-    connect \B \b
-    connect \S \eq0_y
-    connect \Y \mux0_y
-  end
-
-  attribute \src "muxpack_src_b"
-  cell $mux \mux1
-    parameter \WIDTH 2
-    connect \A \mux0_y
-    connect \B \c
-    connect \S \eq1_y
-    connect \Y \y
-  end
-end
-EOT
-
-muxpack
-
-select -assert-count 1 t:$pmux
-select -assert-count 1 t:$pmux a:src=muxpack_src_b|muxpack_src_a %i